Kernel driver w1-uart

Author: Christoph Winklhofer <>


UART 1-Wire bus driver. The driver utilizes the UART interface via the Serial Device Bus to create the 1-Wire timing patterns as described in the document “Using a UART to Implement a 1-Wire Bus Master”.

In short, the UART peripheral must support full-duplex and operate in open-drain mode. The timing patterns are generated by a specific combination of baud-rate and transmitted byte, which corresponds to a 1-Wire read bit, write bit or reset pulse.

For instance the timing pattern for a 1-Wire reset and presence detect uses the baud-rate 9600, i.e. 104.2 us per bit. The transmitted byte 0xf0 over UART (least significant bit first, start-bit low) sets the reset low time for 1-Wire to 521 us. A present 1-Wire device changes the received byte by pulling the line low, which is used by the driver to evaluate the result of the 1-Wire operation.

Similar for a 1-Wire read bit or write bit, which uses the baud-rate 115200, i.e. 8.7 us per bit. The transmitted byte 0x80 is used for a Write-0 operation (low time 69.6us) and the byte 0xff for Read-0, Read-1 and Write-1 (low time 8.7us).

The default baud-rate for reset and presence detection is 9600 and for a 1-Wire read or write operation 115200. In case the actual baud-rate is different from the requested one, the transmitted byte is adapted to generate the 1-Wire timing patterns.


Specify the UART 1-wire bus in the device tree by adding the single child onewire to the serial node (e.g. uart0). For example:

@uart0 {
  onewire {
    compatible = "w1-uart";