00001 /* 00002 Copyright (C) Intel Corp. 2006. All Rights Reserved. 00003 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 00004 develop this 3D driver. 00005 00006 Permission is hereby granted, free of charge, to any person obtaining 00007 a copy of this software and associated documentation files (the 00008 "Software"), to deal in the Software without restriction, including 00009 without limitation the rights to use, copy, modify, merge, publish, 00010 distribute, sublicense, and/or sell copies of the Software, and to 00011 permit persons to whom the Software is furnished to do so, subject to 00012 the following conditions: 00013 00014 The above copyright notice and this permission notice (including the 00015 next paragraph) shall be included in all copies or substantial 00016 portions of the Software. 00017 00018 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 00019 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00020 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 00021 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 00022 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 00023 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 00024 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 00025 00026 **********************************************************************/ 00027 /* 00028 * Authors: 00029 * Keith Whitwell <keith@tungstengraphics.com> 00030 */ 00031 00032 00033 #ifndef BRW_STRUCTS_H 00034 #define BRW_STRUCTS_H 00035 00036 #include "pipe/p_compiler.h" 00037 00038 /* Command packets: 00039 */ 00040 struct header 00041 { 00042 unsigned length:16; 00043 unsigned opcode:16; 00044 }; 00045 00046 00047 union header_union 00048 { 00049 struct header bits; 00050 unsigned dword; 00051 }; 00052 00053 struct brw_3d_control 00054 { 00055 struct 00056 { 00057 unsigned length:8; 00058 unsigned notify_enable:1; 00059 unsigned pad:3; 00060 unsigned wc_flush_enable:1; 00061 unsigned depth_stall_enable:1; 00062 unsigned operation:2; 00063 unsigned opcode:16; 00064 } header; 00065 00066 struct 00067 { 00068 unsigned pad:2; 00069 unsigned dest_addr_type:1; 00070 unsigned dest_addr:29; 00071 } dest; 00072 00073 unsigned dword2; 00074 unsigned dword3; 00075 }; 00076 00077 00078 struct brw_3d_primitive 00079 { 00080 struct 00081 { 00082 unsigned length:8; 00083 unsigned pad:2; 00084 unsigned topology:5; 00085 unsigned indexed:1; 00086 unsigned opcode:16; 00087 } header; 00088 00089 unsigned verts_per_instance; 00090 unsigned start_vert_location; 00091 unsigned instance_count; 00092 unsigned start_instance_location; 00093 unsigned base_vert_location; 00094 }; 00095 00096 /* These seem to be passed around as function args, so it works out 00097 * better to keep them as #defines: 00098 */ 00099 #define BRW_FLUSH_READ_CACHE 0x1 00100 #define BRW_FLUSH_STATE_CACHE 0x2 00101 #define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4 00102 #define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8 00103 00104 struct brw_mi_flush 00105 { 00106 unsigned flags:4; 00107 unsigned pad:12; 00108 unsigned opcode:16; 00109 }; 00110 00111 struct brw_vf_statistics 00112 { 00113 unsigned statistics_enable:1; 00114 unsigned pad:15; 00115 unsigned opcode:16; 00116 }; 00117 00118 00119 00120 struct brw_binding_table_pointers 00121 { 00122 struct header header; 00123 unsigned vs; 00124 unsigned gs; 00125 unsigned clp; 00126 unsigned sf; 00127 unsigned wm; 00128 }; 00129 00130 00131 struct brw_blend_constant_color 00132 { 00133 struct header header; 00134 float blend_constant_color[4]; 00135 }; 00136 00137 00138 struct brw_depthbuffer 00139 { 00140 union header_union header; 00141 00142 union { 00143 struct { 00144 unsigned pitch:18; 00145 unsigned format:3; 00146 unsigned pad:4; 00147 unsigned depth_offset_disable:1; 00148 unsigned tile_walk:1; 00149 unsigned tiled_surface:1; 00150 unsigned pad2:1; 00151 unsigned surface_type:3; 00152 } bits; 00153 unsigned dword; 00154 } dword1; 00155 00156 unsigned dword2_base_addr; 00157 00158 union { 00159 struct { 00160 unsigned pad:1; 00161 unsigned mipmap_layout:1; 00162 unsigned lod:4; 00163 unsigned width:13; 00164 unsigned height:13; 00165 } bits; 00166 unsigned dword; 00167 } dword3; 00168 00169 union { 00170 struct { 00171 unsigned pad:12; 00172 unsigned min_array_element:9; 00173 unsigned depth:11; 00174 } bits; 00175 unsigned dword; 00176 } dword4; 00177 }; 00178 00179 struct brw_drawrect 00180 { 00181 struct header header; 00182 unsigned xmin:16; 00183 unsigned ymin:16; 00184 unsigned xmax:16; 00185 unsigned ymax:16; 00186 unsigned xorg:16; 00187 unsigned yorg:16; 00188 }; 00189 00190 00191 00192 00193 struct brw_global_depth_offset_clamp 00194 { 00195 struct header header; 00196 float depth_offset_clamp; 00197 }; 00198 00199 struct brw_indexbuffer 00200 { 00201 union { 00202 struct 00203 { 00204 unsigned length:8; 00205 unsigned index_format:2; 00206 unsigned cut_index_enable:1; 00207 unsigned pad:5; 00208 unsigned opcode:16; 00209 } bits; 00210 unsigned dword; 00211 00212 } header; 00213 00214 unsigned buffer_start; 00215 unsigned buffer_end; 00216 }; 00217 00218 00219 struct brw_line_stipple 00220 { 00221 struct header header; 00222 00223 struct 00224 { 00225 unsigned pattern:16; 00226 unsigned pad:16; 00227 } bits0; 00228 00229 struct 00230 { 00231 unsigned repeat_count:9; 00232 unsigned pad:7; 00233 unsigned inverse_repeat_count:16; 00234 } bits1; 00235 }; 00236 00237 00238 struct brw_pipelined_state_pointers 00239 { 00240 struct header header; 00241 00242 struct { 00243 unsigned pad:5; 00244 unsigned offset:27; 00245 } vs; 00246 00247 struct 00248 { 00249 unsigned enable:1; 00250 unsigned pad:4; 00251 unsigned offset:27; 00252 } gs; 00253 00254 struct 00255 { 00256 unsigned enable:1; 00257 unsigned pad:4; 00258 unsigned offset:27; 00259 } clp; 00260 00261 struct 00262 { 00263 unsigned pad:5; 00264 unsigned offset:27; 00265 } sf; 00266 00267 struct 00268 { 00269 unsigned pad:5; 00270 unsigned offset:27; 00271 } wm; 00272 00273 struct 00274 { 00275 unsigned pad:5; 00276 unsigned offset:27; /* KW: check me! */ 00277 } cc; 00278 }; 00279 00280 00281 struct brw_polygon_stipple_offset 00282 { 00283 struct header header; 00284 00285 struct { 00286 unsigned y_offset:5; 00287 unsigned pad:3; 00288 unsigned x_offset:5; 00289 unsigned pad0:19; 00290 } bits0; 00291 }; 00292 00293 00294 00295 struct brw_polygon_stipple 00296 { 00297 struct header header; 00298 unsigned stipple[32]; 00299 }; 00300 00301 00302 00303 struct brw_pipeline_select 00304 { 00305 struct 00306 { 00307 unsigned pipeline_select:1; 00308 unsigned pad:15; 00309 unsigned opcode:16; 00310 } header; 00311 }; 00312 00313 00314 struct brw_pipe_control 00315 { 00316 struct 00317 { 00318 unsigned length:8; 00319 unsigned notify_enable:1; 00320 unsigned pad:2; 00321 unsigned instruction_state_cache_flush_enable:1; 00322 unsigned write_cache_flush_enable:1; 00323 unsigned depth_stall_enable:1; 00324 unsigned post_sync_operation:2; 00325 00326 unsigned opcode:16; 00327 } header; 00328 00329 struct 00330 { 00331 unsigned pad:2; 00332 unsigned dest_addr_type:1; 00333 unsigned dest_addr:29; 00334 } bits1; 00335 00336 unsigned data0; 00337 unsigned data1; 00338 }; 00339 00340 00341 struct brw_urb_fence 00342 { 00343 struct 00344 { 00345 unsigned length:8; 00346 unsigned vs_realloc:1; 00347 unsigned gs_realloc:1; 00348 unsigned clp_realloc:1; 00349 unsigned sf_realloc:1; 00350 unsigned vfe_realloc:1; 00351 unsigned cs_realloc:1; 00352 unsigned pad:2; 00353 unsigned opcode:16; 00354 } header; 00355 00356 struct 00357 { 00358 unsigned vs_fence:10; 00359 unsigned gs_fence:10; 00360 unsigned clp_fence:10; 00361 unsigned pad:2; 00362 } bits0; 00363 00364 struct 00365 { 00366 unsigned sf_fence:10; 00367 unsigned vf_fence:10; 00368 unsigned cs_fence:10; 00369 unsigned pad:2; 00370 } bits1; 00371 }; 00372 00373 struct brw_constant_buffer_state /* previously brw_command_streamer */ 00374 { 00375 struct header header; 00376 00377 struct 00378 { 00379 unsigned nr_urb_entries:3; 00380 unsigned pad:1; 00381 unsigned urb_entry_size:5; 00382 unsigned pad0:23; 00383 } bits0; 00384 }; 00385 00386 struct brw_constant_buffer 00387 { 00388 struct 00389 { 00390 unsigned length:8; 00391 unsigned valid:1; 00392 unsigned pad:7; 00393 unsigned opcode:16; 00394 } header; 00395 00396 struct 00397 { 00398 unsigned buffer_length:6; 00399 unsigned buffer_address:26; 00400 } bits0; 00401 }; 00402 00403 struct brw_state_base_address 00404 { 00405 struct header header; 00406 00407 struct 00408 { 00409 unsigned modify_enable:1; 00410 unsigned pad:4; 00411 unsigned general_state_address:27; 00412 } bits0; 00413 00414 struct 00415 { 00416 unsigned modify_enable:1; 00417 unsigned pad:4; 00418 unsigned surface_state_address:27; 00419 } bits1; 00420 00421 struct 00422 { 00423 unsigned modify_enable:1; 00424 unsigned pad:4; 00425 unsigned indirect_object_state_address:27; 00426 } bits2; 00427 00428 struct 00429 { 00430 unsigned modify_enable:1; 00431 unsigned pad:11; 00432 unsigned general_state_upper_bound:20; 00433 } bits3; 00434 00435 struct 00436 { 00437 unsigned modify_enable:1; 00438 unsigned pad:11; 00439 unsigned indirect_object_state_upper_bound:20; 00440 } bits4; 00441 }; 00442 00443 struct brw_state_prefetch 00444 { 00445 struct header header; 00446 00447 struct 00448 { 00449 unsigned prefetch_count:3; 00450 unsigned pad:3; 00451 unsigned prefetch_pointer:26; 00452 } bits0; 00453 }; 00454 00455 struct brw_system_instruction_pointer 00456 { 00457 struct header header; 00458 00459 struct 00460 { 00461 unsigned pad:4; 00462 unsigned system_instruction_pointer:28; 00463 } bits0; 00464 }; 00465 00466 00467 00468 00469 /* State structs for the various fixed function units: 00470 */ 00471 00472 00473 struct thread0 00474 { 00475 unsigned pad0:1; 00476 unsigned grf_reg_count:3; 00477 unsigned pad1:2; 00478 unsigned kernel_start_pointer:26; 00479 }; 00480 00481 struct thread1 00482 { 00483 unsigned ext_halt_exception_enable:1; 00484 unsigned sw_exception_enable:1; 00485 unsigned mask_stack_exception_enable:1; 00486 unsigned timeout_exception_enable:1; 00487 unsigned illegal_op_exception_enable:1; 00488 unsigned pad0:3; 00489 unsigned depth_coef_urb_read_offset:6; /* WM only */ 00490 unsigned pad1:2; 00491 unsigned floating_point_mode:1; 00492 unsigned thread_priority:1; 00493 unsigned binding_table_entry_count:8; 00494 unsigned pad3:5; 00495 unsigned single_program_flow:1; 00496 }; 00497 00498 struct thread2 00499 { 00500 unsigned per_thread_scratch_space:4; 00501 unsigned pad0:6; 00502 unsigned scratch_space_base_pointer:22; 00503 }; 00504 00505 00506 struct thread3 00507 { 00508 unsigned dispatch_grf_start_reg:4; 00509 unsigned urb_entry_read_offset:6; 00510 unsigned pad0:1; 00511 unsigned urb_entry_read_length:6; 00512 unsigned pad1:1; 00513 unsigned const_urb_entry_read_offset:6; 00514 unsigned pad2:1; 00515 unsigned const_urb_entry_read_length:6; 00516 unsigned pad3:1; 00517 }; 00518 00519 00520 00521 struct brw_clip_unit_state 00522 { 00523 struct thread0 thread0; 00524 struct 00525 { 00526 unsigned pad0:7; 00527 unsigned sw_exception_enable:1; 00528 unsigned pad1:3; 00529 unsigned mask_stack_exception_enable:1; 00530 unsigned pad2:1; 00531 unsigned illegal_op_exception_enable:1; 00532 unsigned pad3:2; 00533 unsigned floating_point_mode:1; 00534 unsigned thread_priority:1; 00535 unsigned binding_table_entry_count:8; 00536 unsigned pad4:5; 00537 unsigned single_program_flow:1; 00538 } thread1; 00539 00540 struct thread2 thread2; 00541 struct thread3 thread3; 00542 00543 struct 00544 { 00545 unsigned pad0:9; 00546 unsigned gs_output_stats:1; /* not always */ 00547 unsigned stats_enable:1; 00548 unsigned nr_urb_entries:7; 00549 unsigned pad1:1; 00550 unsigned urb_entry_allocation_size:5; 00551 unsigned pad2:1; 00552 unsigned max_threads:1; /* may be less */ 00553 unsigned pad3:6; 00554 } thread4; 00555 00556 struct 00557 { 00558 unsigned pad0:13; 00559 unsigned clip_mode:3; 00560 unsigned userclip_enable_flags:8; 00561 unsigned userclip_must_clip:1; 00562 unsigned pad1:1; 00563 unsigned guard_band_enable:1; 00564 unsigned viewport_z_clip_enable:1; 00565 unsigned viewport_xy_clip_enable:1; 00566 unsigned vertex_position_space:1; 00567 unsigned api_mode:1; 00568 unsigned pad2:1; 00569 } clip5; 00570 00571 struct 00572 { 00573 unsigned pad0:5; 00574 unsigned clipper_viewport_state_ptr:27; 00575 } clip6; 00576 00577 00578 float viewport_xmin; 00579 float viewport_xmax; 00580 float viewport_ymin; 00581 float viewport_ymax; 00582 }; 00583 00584 00585 00586 struct brw_cc_unit_state 00587 { 00588 struct 00589 { 00590 unsigned pad0:3; 00591 unsigned bf_stencil_pass_depth_pass_op:3; 00592 unsigned bf_stencil_pass_depth_fail_op:3; 00593 unsigned bf_stencil_fail_op:3; 00594 unsigned bf_stencil_func:3; 00595 unsigned bf_stencil_enable:1; 00596 unsigned pad1:2; 00597 unsigned stencil_write_enable:1; 00598 unsigned stencil_pass_depth_pass_op:3; 00599 unsigned stencil_pass_depth_fail_op:3; 00600 unsigned stencil_fail_op:3; 00601 unsigned stencil_func:3; 00602 unsigned stencil_enable:1; 00603 } cc0; 00604 00605 00606 struct 00607 { 00608 unsigned bf_stencil_ref:8; 00609 unsigned stencil_write_mask:8; 00610 unsigned stencil_test_mask:8; 00611 unsigned stencil_ref:8; 00612 } cc1; 00613 00614 00615 struct 00616 { 00617 unsigned logicop_enable:1; 00618 unsigned pad0:10; 00619 unsigned depth_write_enable:1; 00620 unsigned depth_test_function:3; 00621 unsigned depth_test:1; 00622 unsigned bf_stencil_write_mask:8; 00623 unsigned bf_stencil_test_mask:8; 00624 } cc2; 00625 00626 00627 struct 00628 { 00629 unsigned pad0:8; 00630 unsigned alpha_test_func:3; 00631 unsigned alpha_test:1; 00632 unsigned blend_enable:1; 00633 unsigned ia_blend_enable:1; 00634 unsigned pad1:1; 00635 unsigned alpha_test_format:1; 00636 unsigned pad2:16; 00637 } cc3; 00638 00639 struct 00640 { 00641 unsigned pad0:5; 00642 unsigned cc_viewport_state_offset:27; 00643 } cc4; 00644 00645 struct 00646 { 00647 unsigned pad0:2; 00648 unsigned ia_dest_blend_factor:5; 00649 unsigned ia_src_blend_factor:5; 00650 unsigned ia_blend_function:3; 00651 unsigned statistics_enable:1; 00652 unsigned logicop_func:4; 00653 unsigned pad1:11; 00654 unsigned dither_enable:1; 00655 } cc5; 00656 00657 struct 00658 { 00659 unsigned clamp_post_alpha_blend:1; 00660 unsigned clamp_pre_alpha_blend:1; 00661 unsigned clamp_range:2; 00662 unsigned pad0:11; 00663 unsigned y_dither_offset:2; 00664 unsigned x_dither_offset:2; 00665 unsigned dest_blend_factor:5; 00666 unsigned src_blend_factor:5; 00667 unsigned blend_function:3; 00668 } cc6; 00669 00670 struct { 00671 union { 00672 float f; 00673 ubyte ub[4]; 00674 } alpha_ref; 00675 } cc7; 00676 }; 00677 00678 00679 00680 struct brw_sf_unit_state 00681 { 00682 struct thread0 thread0; 00683 struct thread1 thread1; 00684 struct thread2 thread2; 00685 struct thread3 thread3; 00686 00687 struct 00688 { 00689 unsigned pad0:10; 00690 unsigned stats_enable:1; 00691 unsigned nr_urb_entries:7; 00692 unsigned pad1:1; 00693 unsigned urb_entry_allocation_size:5; 00694 unsigned pad2:1; 00695 unsigned max_threads:6; 00696 unsigned pad3:1; 00697 } thread4; 00698 00699 struct 00700 { 00701 unsigned front_winding:1; 00702 unsigned viewport_transform:1; 00703 unsigned pad0:3; 00704 unsigned sf_viewport_state_offset:27; 00705 } sf5; 00706 00707 struct 00708 { 00709 unsigned pad0:9; 00710 unsigned dest_org_vbias:4; 00711 unsigned dest_org_hbias:4; 00712 unsigned scissor:1; 00713 unsigned disable_2x2_trifilter:1; 00714 unsigned disable_zero_pix_trifilter:1; 00715 unsigned point_rast_rule:2; 00716 unsigned line_endcap_aa_region_width:2; 00717 unsigned line_width:4; 00718 unsigned fast_scissor_disable:1; 00719 unsigned cull_mode:2; 00720 unsigned aa_enable:1; 00721 } sf6; 00722 00723 struct 00724 { 00725 unsigned point_size:11; 00726 unsigned use_point_size_state:1; 00727 unsigned subpixel_precision:1; 00728 unsigned sprite_point:1; 00729 unsigned pad0:11; 00730 unsigned trifan_pv:2; 00731 unsigned linestrip_pv:2; 00732 unsigned tristrip_pv:2; 00733 unsigned line_last_pixel_enable:1; 00734 } sf7; 00735 00736 }; 00737 00738 00739 struct brw_gs_unit_state 00740 { 00741 struct thread0 thread0; 00742 struct thread1 thread1; 00743 struct thread2 thread2; 00744 struct thread3 thread3; 00745 00746 struct 00747 { 00748 unsigned pad0:10; 00749 unsigned stats_enable:1; 00750 unsigned nr_urb_entries:7; 00751 unsigned pad1:1; 00752 unsigned urb_entry_allocation_size:5; 00753 unsigned pad2:1; 00754 unsigned max_threads:1; 00755 unsigned pad3:6; 00756 } thread4; 00757 00758 struct 00759 { 00760 unsigned sampler_count:3; 00761 unsigned pad0:2; 00762 unsigned sampler_state_pointer:27; 00763 } gs5; 00764 00765 00766 struct 00767 { 00768 unsigned max_vp_index:4; 00769 unsigned pad0:26; 00770 unsigned reorder_enable:1; 00771 unsigned pad1:1; 00772 } gs6; 00773 }; 00774 00775 00776 struct brw_vs_unit_state 00777 { 00778 struct thread0 thread0; 00779 struct thread1 thread1; 00780 struct thread2 thread2; 00781 struct thread3 thread3; 00782 00783 struct 00784 { 00785 unsigned pad0:10; 00786 unsigned stats_enable:1; 00787 unsigned nr_urb_entries:7; 00788 unsigned pad1:1; 00789 unsigned urb_entry_allocation_size:5; 00790 unsigned pad2:1; 00791 unsigned max_threads:4; 00792 unsigned pad3:3; 00793 } thread4; 00794 00795 struct 00796 { 00797 unsigned sampler_count:3; 00798 unsigned pad0:2; 00799 unsigned sampler_state_pointer:27; 00800 } vs5; 00801 00802 struct 00803 { 00804 unsigned vs_enable:1; 00805 unsigned vert_cache_disable:1; 00806 unsigned pad0:30; 00807 } vs6; 00808 }; 00809 00810 00811 struct brw_wm_unit_state 00812 { 00813 struct thread0 thread0; 00814 struct thread1 thread1; 00815 struct thread2 thread2; 00816 struct thread3 thread3; 00817 00818 struct { 00819 unsigned stats_enable:1; 00820 unsigned pad0:1; 00821 unsigned sampler_count:3; 00822 unsigned sampler_state_pointer:27; 00823 } wm4; 00824 00825 struct 00826 { 00827 unsigned enable_8_pix:1; 00828 unsigned enable_16_pix:1; 00829 unsigned enable_32_pix:1; 00830 unsigned pad0:7; 00831 unsigned legacy_global_depth_bias:1; 00832 unsigned line_stipple:1; 00833 unsigned depth_offset:1; 00834 unsigned polygon_stipple:1; 00835 unsigned line_aa_region_width:2; 00836 unsigned line_endcap_aa_region_width:2; 00837 unsigned early_depth_test:1; 00838 unsigned thread_dispatch_enable:1; 00839 unsigned program_uses_depth:1; 00840 unsigned program_computes_depth:1; 00841 unsigned program_uses_killpixel:1; 00842 unsigned legacy_line_rast: 1; 00843 unsigned pad1:1; 00844 unsigned max_threads:6; 00845 unsigned pad2:1; 00846 } wm5; 00847 00848 float global_depth_offset_constant; 00849 float global_depth_offset_scale; 00850 }; 00851 00852 struct brw_sampler_default_color { 00853 float color[4]; 00854 }; 00855 00856 struct brw_sampler_state 00857 { 00858 00859 struct 00860 { 00861 unsigned shadow_function:3; 00862 unsigned lod_bias:11; 00863 unsigned min_filter:3; 00864 unsigned mag_filter:3; 00865 unsigned mip_filter:2; 00866 unsigned base_level:5; 00867 unsigned pad:1; 00868 unsigned lod_preclamp:1; 00869 unsigned default_color_mode:1; 00870 unsigned pad0:1; 00871 unsigned disable:1; 00872 } ss0; 00873 00874 struct 00875 { 00876 unsigned r_wrap_mode:3; 00877 unsigned t_wrap_mode:3; 00878 unsigned s_wrap_mode:3; 00879 unsigned pad:3; 00880 unsigned max_lod:10; 00881 unsigned min_lod:10; 00882 } ss1; 00883 00884 00885 struct 00886 { 00887 unsigned pad:5; 00888 unsigned default_color_pointer:27; 00889 } ss2; 00890 00891 struct 00892 { 00893 unsigned pad:19; 00894 unsigned max_aniso:3; 00895 unsigned chroma_key_mode:1; 00896 unsigned chroma_key_index:2; 00897 unsigned chroma_key_enable:1; 00898 unsigned monochrome_filter_width:3; 00899 unsigned monochrome_filter_height:3; 00900 } ss3; 00901 }; 00902 00903 00904 struct brw_clipper_viewport 00905 { 00906 float xmin; 00907 float xmax; 00908 float ymin; 00909 float ymax; 00910 }; 00911 00912 struct brw_cc_viewport 00913 { 00914 float min_depth; 00915 float max_depth; 00916 }; 00917 00918 struct brw_sf_viewport 00919 { 00920 struct { 00921 float m00; 00922 float m11; 00923 float m22; 00924 float m30; 00925 float m31; 00926 float m32; 00927 } viewport; 00928 00929 struct { 00930 short xmin; 00931 short ymin; 00932 short xmax; 00933 short ymax; 00934 } scissor; 00935 }; 00936 00937 /* Documented in the subsystem/shared-functions/sampler chapter... 00938 */ 00939 struct brw_surface_state 00940 { 00941 struct { 00942 unsigned cube_pos_z:1; 00943 unsigned cube_neg_z:1; 00944 unsigned cube_pos_y:1; 00945 unsigned cube_neg_y:1; 00946 unsigned cube_pos_x:1; 00947 unsigned cube_neg_x:1; 00948 unsigned pad:4; 00949 unsigned mipmap_layout_mode:1; 00950 unsigned vert_line_stride_ofs:1; 00951 unsigned vert_line_stride:1; 00952 unsigned color_blend:1; 00953 unsigned writedisable_blue:1; 00954 unsigned writedisable_green:1; 00955 unsigned writedisable_red:1; 00956 unsigned writedisable_alpha:1; 00957 unsigned surface_format:9; 00958 unsigned data_return_format:1; 00959 unsigned pad0:1; 00960 unsigned surface_type:3; 00961 } ss0; 00962 00963 struct { 00964 unsigned base_addr; 00965 } ss1; 00966 00967 struct { 00968 unsigned pad:2; 00969 unsigned mip_count:4; 00970 unsigned width:13; 00971 unsigned height:13; 00972 } ss2; 00973 00974 struct { 00975 unsigned tile_walk:1; 00976 unsigned tiled_surface:1; 00977 unsigned pad:1; 00978 unsigned pitch:18; 00979 unsigned depth:11; 00980 } ss3; 00981 00982 struct { 00983 unsigned pad:19; 00984 unsigned min_array_elt:9; 00985 unsigned min_lod:4; 00986 } ss4; 00987 }; 00988 00989 00990 00991 struct brw_vertex_buffer_state 00992 { 00993 struct { 00994 unsigned pitch:11; 00995 unsigned pad:15; 00996 unsigned access_type:1; 00997 unsigned vb_index:5; 00998 } vb0; 00999 01000 unsigned start_addr; 01001 unsigned max_index; 01002 #if 1 01003 unsigned instance_data_step_rate; /* not included for sequential/random vertices? */ 01004 #endif 01005 }; 01006 01007 #define BRW_VBP_MAX 17 01008 01009 struct brw_vb_array_state { 01010 struct header header; 01011 struct brw_vertex_buffer_state vb[BRW_VBP_MAX]; 01012 }; 01013 01014 01015 struct brw_vertex_element_state 01016 { 01017 struct 01018 { 01019 unsigned src_offset:11; 01020 unsigned pad:5; 01021 unsigned src_format:9; 01022 unsigned pad0:1; 01023 unsigned valid:1; 01024 unsigned vertex_buffer_index:5; 01025 } ve0; 01026 01027 struct 01028 { 01029 unsigned dst_offset:8; 01030 unsigned pad:8; 01031 unsigned vfcomponent3:4; 01032 unsigned vfcomponent2:4; 01033 unsigned vfcomponent1:4; 01034 unsigned vfcomponent0:4; 01035 } ve1; 01036 }; 01037 01038 #define BRW_VEP_MAX 18 01039 01040 struct brw_vertex_element_packet { 01041 struct header header; 01042 struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */ 01043 }; 01044 01045 01046 struct brw_urb_immediate { 01047 unsigned opcode:4; 01048 unsigned offset:6; 01049 unsigned swizzle_control:2; 01050 unsigned pad:1; 01051 unsigned allocate:1; 01052 unsigned used:1; 01053 unsigned complete:1; 01054 unsigned response_length:4; 01055 unsigned msg_length:4; 01056 unsigned msg_target:4; 01057 unsigned pad1:3; 01058 unsigned end_of_thread:1; 01059 }; 01060 01061 /* Instruction format for the execution units: 01062 */ 01063 01064 struct brw_instruction 01065 { 01066 struct 01067 { 01068 unsigned opcode:7; 01069 unsigned pad:1; 01070 unsigned access_mode:1; 01071 unsigned mask_control:1; 01072 unsigned dependency_control:2; 01073 unsigned compression_control:2; 01074 unsigned thread_control:2; 01075 unsigned predicate_control:4; 01076 unsigned predicate_inverse:1; 01077 unsigned execution_size:3; 01078 unsigned destreg__conditonalmod:4; /* destreg - send, conditionalmod - others */ 01079 unsigned pad0:2; 01080 unsigned debug_control:1; 01081 unsigned saturate:1; 01082 } header; 01083 01084 union { 01085 struct 01086 { 01087 unsigned dest_reg_file:2; 01088 unsigned dest_reg_type:3; 01089 unsigned src0_reg_file:2; 01090 unsigned src0_reg_type:3; 01091 unsigned src1_reg_file:2; 01092 unsigned src1_reg_type:3; 01093 unsigned pad:1; 01094 unsigned dest_subreg_nr:5; 01095 unsigned dest_reg_nr:8; 01096 unsigned dest_horiz_stride:2; 01097 unsigned dest_address_mode:1; 01098 } da1; 01099 01100 struct 01101 { 01102 unsigned dest_reg_file:2; 01103 unsigned dest_reg_type:3; 01104 unsigned src0_reg_file:2; 01105 unsigned src0_reg_type:3; 01106 unsigned pad:6; 01107 int dest_indirect_offset:10; /* offset against the deref'd address reg */ 01108 unsigned dest_subreg_nr:3; /* subnr for the address reg a0.x */ 01109 unsigned dest_horiz_stride:2; 01110 unsigned dest_address_mode:1; 01111 } ia1; 01112 01113 struct 01114 { 01115 unsigned dest_reg_file:2; 01116 unsigned dest_reg_type:3; 01117 unsigned src0_reg_file:2; 01118 unsigned src0_reg_type:3; 01119 unsigned src1_reg_file:2; 01120 unsigned src1_reg_type:3; 01121 unsigned pad0:1; 01122 unsigned dest_writemask:4; 01123 unsigned dest_subreg_nr:1; 01124 unsigned dest_reg_nr:8; 01125 unsigned pad1:2; 01126 unsigned dest_address_mode:1; 01127 } da16; 01128 01129 struct 01130 { 01131 unsigned dest_reg_file:2; 01132 unsigned dest_reg_type:3; 01133 unsigned src0_reg_file:2; 01134 unsigned src0_reg_type:3; 01135 unsigned pad0:6; 01136 unsigned dest_writemask:4; 01137 int dest_indirect_offset:6; 01138 unsigned dest_subreg_nr:3; 01139 unsigned pad1:2; 01140 unsigned dest_address_mode:1; 01141 } ia16; 01142 } bits1; 01143 01144 01145 union { 01146 struct 01147 { 01148 unsigned src0_subreg_nr:5; 01149 unsigned src0_reg_nr:8; 01150 unsigned src0_abs:1; 01151 unsigned src0_negate:1; 01152 unsigned src0_address_mode:1; 01153 unsigned src0_horiz_stride:2; 01154 unsigned src0_width:3; 01155 unsigned src0_vert_stride:4; 01156 unsigned flag_reg_nr:1; 01157 unsigned pad:6; 01158 } da1; 01159 01160 struct 01161 { 01162 int src0_indirect_offset:10; 01163 unsigned src0_subreg_nr:3; 01164 unsigned src0_abs:1; 01165 unsigned src0_negate:1; 01166 unsigned src0_address_mode:1; 01167 unsigned src0_horiz_stride:2; 01168 unsigned src0_width:3; 01169 unsigned src0_vert_stride:4; 01170 unsigned flag_reg_nr:1; 01171 unsigned pad:6; 01172 } ia1; 01173 01174 struct 01175 { 01176 unsigned src0_swz_x:2; 01177 unsigned src0_swz_y:2; 01178 unsigned src0_subreg_nr:1; 01179 unsigned src0_reg_nr:8; 01180 unsigned src0_abs:1; 01181 unsigned src0_negate:1; 01182 unsigned src0_address_mode:1; 01183 unsigned src0_swz_z:2; 01184 unsigned src0_swz_w:2; 01185 unsigned pad0:1; 01186 unsigned src0_vert_stride:4; 01187 unsigned flag_reg_nr:1; 01188 unsigned pad1:6; 01189 } da16; 01190 01191 struct 01192 { 01193 unsigned src0_swz_x:2; 01194 unsigned src0_swz_y:2; 01195 int src0_indirect_offset:6; 01196 unsigned src0_subreg_nr:3; 01197 unsigned src0_abs:1; 01198 unsigned src0_negate:1; 01199 unsigned src0_address_mode:1; 01200 unsigned src0_swz_z:2; 01201 unsigned src0_swz_w:2; 01202 unsigned pad0:1; 01203 unsigned src0_vert_stride:4; 01204 unsigned flag_reg_nr:1; 01205 unsigned pad1:6; 01206 } ia16; 01207 01208 } bits2; 01209 01210 union 01211 { 01212 struct 01213 { 01214 unsigned src1_subreg_nr:5; 01215 unsigned src1_reg_nr:8; 01216 unsigned src1_abs:1; 01217 unsigned src1_negate:1; 01218 unsigned pad:1; 01219 unsigned src1_horiz_stride:2; 01220 unsigned src1_width:3; 01221 unsigned src1_vert_stride:4; 01222 unsigned pad0:7; 01223 } da1; 01224 01225 struct 01226 { 01227 unsigned src1_swz_x:2; 01228 unsigned src1_swz_y:2; 01229 unsigned src1_subreg_nr:1; 01230 unsigned src1_reg_nr:8; 01231 unsigned src1_abs:1; 01232 unsigned src1_negate:1; 01233 unsigned pad0:1; 01234 unsigned src1_swz_z:2; 01235 unsigned src1_swz_w:2; 01236 unsigned pad1:1; 01237 unsigned src1_vert_stride:4; 01238 unsigned pad2:7; 01239 } da16; 01240 01241 struct 01242 { 01243 int src1_indirect_offset:10; 01244 unsigned src1_subreg_nr:3; 01245 unsigned src1_abs:1; 01246 unsigned src1_negate:1; 01247 unsigned pad0:1; 01248 unsigned src1_horiz_stride:2; 01249 unsigned src1_width:3; 01250 unsigned src1_vert_stride:4; 01251 unsigned flag_reg_nr:1; 01252 unsigned pad1:6; 01253 } ia1; 01254 01255 struct 01256 { 01257 unsigned src1_swz_x:2; 01258 unsigned src1_swz_y:2; 01259 int src1_indirect_offset:6; 01260 unsigned src1_subreg_nr:3; 01261 unsigned src1_abs:1; 01262 unsigned src1_negate:1; 01263 unsigned pad0:1; 01264 unsigned src1_swz_z:2; 01265 unsigned src1_swz_w:2; 01266 unsigned pad1:1; 01267 unsigned src1_vert_stride:4; 01268 unsigned flag_reg_nr:1; 01269 unsigned pad2:6; 01270 } ia16; 01271 01272 01273 struct 01274 { 01275 int jump_count:16; /* note: signed */ 01276 unsigned pop_count:4; 01277 unsigned pad0:12; 01278 } if_else; 01279 01280 struct { 01281 unsigned function:4; 01282 unsigned int_type:1; 01283 unsigned precision:1; 01284 unsigned saturate:1; 01285 unsigned data_type:1; 01286 unsigned pad0:8; 01287 unsigned response_length:4; 01288 unsigned msg_length:4; 01289 unsigned msg_target:4; 01290 unsigned pad1:3; 01291 unsigned end_of_thread:1; 01292 } math; 01293 01294 struct { 01295 unsigned binding_table_index:8; 01296 unsigned sampler:4; 01297 unsigned return_format:2; 01298 unsigned msg_type:2; 01299 unsigned response_length:4; 01300 unsigned msg_length:4; 01301 unsigned msg_target:4; 01302 unsigned pad1:3; 01303 unsigned end_of_thread:1; 01304 } sampler; 01305 01306 struct brw_urb_immediate urb; 01307 01308 struct { 01309 unsigned binding_table_index:8; 01310 unsigned msg_control:4; 01311 unsigned msg_type:2; 01312 unsigned target_cache:2; 01313 unsigned response_length:4; 01314 unsigned msg_length:4; 01315 unsigned msg_target:4; 01316 unsigned pad1:3; 01317 unsigned end_of_thread:1; 01318 } dp_read; 01319 01320 struct { 01321 unsigned binding_table_index:8; 01322 unsigned msg_control:3; 01323 unsigned pixel_scoreboard_clear:1; 01324 unsigned msg_type:3; 01325 unsigned send_commit_msg:1; 01326 unsigned response_length:4; 01327 unsigned msg_length:4; 01328 unsigned msg_target:4; 01329 unsigned pad1:3; 01330 unsigned end_of_thread:1; 01331 } dp_write; 01332 01333 struct { 01334 unsigned pad:16; 01335 unsigned response_length:4; 01336 unsigned msg_length:4; 01337 unsigned msg_target:4; 01338 unsigned pad1:3; 01339 unsigned end_of_thread:1; 01340 } generic; 01341 01342 int d; 01343 unsigned ud; 01344 } bits3; 01345 }; 01346 01347 01348 #endif
1.5.4