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00030 #ifndef _I830_COMMON_H_
00031 #define _I830_COMMON_H_
00032
00033
00034 #define I830_NR_TEX_REGIONS 255
00035 #define I830_LOG_MIN_TEX_REGION_SIZE 14
00036
00037
00038
00039
00040
00041 #define DRM_I830_INIT 0x00
00042 #define DRM_I830_FLUSH 0x01
00043 #define DRM_I830_FLIP 0x02
00044 #define DRM_I830_BATCHBUFFER 0x03
00045 #define DRM_I830_IRQ_EMIT 0x04
00046 #define DRM_I830_IRQ_WAIT 0x05
00047 #define DRM_I830_GETPARAM 0x06
00048 #define DRM_I830_SETPARAM 0x07
00049 #define DRM_I830_ALLOC 0x08
00050 #define DRM_I830_FREE 0x09
00051 #define DRM_I830_INIT_HEAP 0x0a
00052 #define DRM_I830_CMDBUFFER 0x0b
00053 #define DRM_I830_DESTROY_HEAP 0x0c
00054 #define DRM_I830_SET_VBLANK_PIPE 0x0d
00055 #define DRM_I830_GET_VBLANK_PIPE 0x0e
00056 #define DRM_I830_MMIO 0x10
00057
00058 typedef struct {
00059 enum {
00060 I830_INIT_DMA = 0x01,
00061 I830_CLEANUP_DMA = 0x02,
00062 I830_RESUME_DMA = 0x03
00063 } func;
00064 unsigned int mmio_offset;
00065 int sarea_priv_offset;
00066 unsigned int ring_start;
00067 unsigned int ring_end;
00068 unsigned int ring_size;
00069 unsigned int front_offset;
00070 unsigned int back_offset;
00071 unsigned int depth_offset;
00072 unsigned int w;
00073 unsigned int h;
00074 unsigned int pitch;
00075 unsigned int pitch_bits;
00076 unsigned int back_pitch;
00077 unsigned int depth_pitch;
00078 unsigned int cpp;
00079 unsigned int chipset;
00080 } drmI830Init;
00081
00082 typedef struct {
00083 drmTextureRegion texList[I830_NR_TEX_REGIONS+1];
00084 int last_upload;
00085 int last_enqueue;
00086 int last_dispatch;
00087 int ctxOwner;
00089 int texAge;
00090 int pf_enabled;
00091 int pf_active;
00092 int pf_current_page;
00093 int perf_boxes;
00094 int width, height;
00095
00096 drm_handle_t front_handle;
00097 int front_offset;
00098 int front_size;
00099
00100 drm_handle_t back_handle;
00101 int back_offset;
00102 int back_size;
00103
00104 drm_handle_t depth_handle;
00105 int depth_offset;
00106 int depth_size;
00107
00108 drm_handle_t tex_handle;
00109 int tex_offset;
00110 int tex_size;
00111 int log_tex_granularity;
00112 int pitch;
00113 int rotation;
00114 int rotated_offset;
00115 int rotated_size;
00116 int rotated_pitch;
00117 int virtualX, virtualY;
00118
00119 unsigned int front_tiled;
00120 unsigned int back_tiled;
00121 unsigned int depth_tiled;
00122 unsigned int rotated_tiled;
00123 unsigned int rotated2_tiled;
00124
00125 int planeA_x;
00126 int planeA_y;
00127 int planeA_w;
00128 int planeA_h;
00129 int planeB_x;
00130 int planeB_y;
00131 int planeB_w;
00132 int planeB_h;
00133
00134
00135 drm_handle_t third_handle;
00136 int third_offset;
00137 int third_size;
00138 unsigned int third_tiled;
00139
00140
00141
00142
00143
00144 unsigned int front_bo_handle;
00145 unsigned int back_bo_handle;
00146 unsigned int third_bo_handle;
00147 unsigned int depth_bo_handle;
00148 } drmI830Sarea;
00149
00150
00151
00152 #define I830_BOX_RING_EMPTY 0x1
00153 #define I830_BOX_FLIP 0x2
00154 #define I830_BOX_WAIT 0x4
00155 #define I830_BOX_TEXTURE_LOAD 0x8
00156 #define I830_BOX_LOST_CONTEXT 0x10
00157
00158
00159 typedef struct {
00160 int start;
00161 int used;
00162 int DR1;
00163 int DR4;
00164 int num_cliprects;
00165 drm_clip_rect_t *cliprects;
00166 } drmI830BatchBuffer;
00167
00168 typedef struct {
00169 char *buf;
00170 int sz;
00171 int DR1;
00172 int DR4;
00173 int num_cliprects;
00174 drm_clip_rect_t *cliprects;
00175 } drmI830CmdBuffer;
00176
00177 typedef struct {
00178 int *irq_seq;
00179 } drmI830IrqEmit;
00180
00181 typedef struct {
00182 int irq_seq;
00183 } drmI830IrqWait;
00184
00185 typedef struct {
00186 int param;
00187 int *value;
00188 } drmI830GetParam;
00189
00190 #define I830_PARAM_IRQ_ACTIVE 1
00191 #define I830_PARAM_ALLOW_BATCHBUFFER 2
00192
00193 typedef struct {
00194 int param;
00195 int value;
00196 } drmI830SetParam;
00197
00198 #define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1
00199 #define I830_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
00200 #define I830_SETPARAM_ALLOW_BATCHBUFFER 3
00201
00202
00203
00204
00205 #define I830_MEM_REGION_AGP 1
00206
00207 typedef struct {
00208 int region;
00209 int alignment;
00210 int size;
00211 int *region_offset;
00212 } drmI830MemAlloc;
00213
00214 typedef struct {
00215 int region;
00216 int region_offset;
00217 } drmI830MemFree;
00218
00219 typedef struct {
00220 int region;
00221 int size;
00222 int start;
00223 } drmI830MemInitHeap;
00224
00225 typedef struct {
00226 int region;
00227 } drmI830MemDestroyHeap;
00228
00229 #define DRM_I830_VBLANK_PIPE_A 1
00230 #define DRM_I830_VBLANK_PIPE_B 2
00231
00232 typedef struct {
00233 int pipe;
00234 } drmI830VBlankPipe;
00235
00236 #define MMIO_READ 0
00237 #define MMIO_WRITE 1
00238
00239 #define MMIO_REGS_IA_PRIMATIVES_COUNT 0
00240 #define MMIO_REGS_IA_VERTICES_COUNT 1
00241 #define MMIO_REGS_VS_INVOCATION_COUNT 2
00242 #define MMIO_REGS_GS_PRIMITIVES_COUNT 3
00243 #define MMIO_REGS_GS_INVOCATION_COUNT 4
00244 #define MMIO_REGS_CL_PRIMITIVES_COUNT 5
00245 #define MMIO_REGS_CL_INVOCATION_COUNT 6
00246 #define MMIO_REGS_PS_INVOCATION_COUNT 7
00247 #define MMIO_REGS_PS_DEPTH_COUNT 8
00248
00249 typedef struct {
00250 unsigned int read_write:1;
00251 unsigned int reg:31;
00252 void __user *data;
00253 } drmI830MMIO;
00254
00255 #endif