05:35topendnick: FL4SHK[m]: open source yosys synthesis driver for xilinx and altera boards would be fun.
11:44topendnick: I am actually sorry, i am sure MrCooper did not mean harm to me (instead was just concerned what to respond to possible red hat clients/users, as to why one guy is so rude), but likely you realized i am correct , what i think you mean that second subtraction results in one constant in polderan, constant is just like 256 a real power, so adding both lengths to constant , or constant to both
11:44topendnick: lengths would do the needed, but i have another algorithm from old times that is my last., that one inverts by subtracting over the constant to a higher power flipping one element yielding the *2 of length instead, and to avoid division or bitshift there is little more steps. Even though i invented those algorithms over long period of work and i worked on preparing myself for FPGA's
11:44topendnick: upfront, and i show some kind of form, I am still clueless about how you do things with your teams, so you must be extremely passionately working, the code works well but is very large to do the needed functionality on goguma , so your team is very talented too, I do not want to join your efforts , cause you upseted me too much, but talent and spirit you have.
11:54topendnick: I can say you try to defend your actions and life as much as i do, and i have liked the gpu channels the best , serious people and no visible narcissist traits when looking at the pics of the teams involved, cause i can spot danger right away when there is something wrong in the facelines, with you it's fine , but i have beef with many other narcissists, it's not a beef they abuse me in
11:54topendnick: real ways, but let it be, everyone finally gets their sanctions i assume, yes you do not deserve to be sanctioned theres no need to.
12:06topendnick: i looked at the boards of enclustra, trenz and arrow tech with extreme respect towards designers, it's a real dream come trough engineering, so in the future i plan to get something from their lineups, i actually have no doubts that those people have worked hard in central europe and usa and are blessed with spectacular talent.
12:24FL4SHK[m]: topendnick: so I'm not really an FPGA compiler developer
12:24FL4SHK[m]: oh but
12:24FL4SHK[m]: yosys can synth for 7 series Xilinx FPGAs already
12:26FL4SHK[m]: No idea if it can synth for any Altera parts
12:40topendnick: ok, yes i saw something as well, i worked on ASIC hdl flattenings through the yices2 yosys solver and on hard drive i saw something that they do initialize for some xilinx'es. So i had ideas how to expose similar methods on fpga's but i need to recap a bit, i worked alot but it was little while ago like 3years the last.
12:51FL4SHK[m]: topendnick: I use yosys's assertion-based formal verification for some of my testing
12:52FL4SHK[m]: especially for stuff like my integer divider module
12:52FL4SHK[m]: or my count leading zeros module
12:53topendnick: lot of this is still on the internet, so i need to refetch those things, i had pdf that showed what altera xilinx luts and dsp blocks look like, so there is one adder and full 32bit reg , so already say the cyclon 5 came with extreme resources. Technically they would perform better than asics with similar code but may need synthesis changes.
12:54topendnick: so dsp blocks are hw multipliers , i have some vague memory about those things.
14:34zmike: mareko pepp: is one of you able to figure out the radeonsi failures in https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29841 ?
15:14pepp: zmike: I'll take a look
15:15zmike: pepp: awesome, thanks
15:28pepp: zmike: draw-pixels only fails with "-fbo" and GL_STENCIL_INDEX, odd
15:28zmike: yes, very
15:31pepp: zmike: MESA_SHADER_CACHE_DISABLE=1 fixes it
15:31zmike: 🤕