00:28 DemiMarie: How big of a hit do Intel and AMD take when rendering to linear buffers?
02:01 mareko: DemiMarie: I'm guessing -75%
02:03 DemiMarie: mareko: what about with a copy to linear and back?
02:04 DemiMarie: I’m finding validating nonlinear buffers to be a nightmare.
02:11 mareko: DemiMarie: if you use the gfx pipeline, -75% regardless of how you do it
02:12 DemiMarie: mareko: what about if I use a copy engine?
02:13 mareko: DemiMarie: -90% if the copy engine is 10x slower than VRAM (the copy engine is meant to be for copies over PCIe, which is ~20x slower than VRAM)
02:13 DemiMarie: mareko: dang it!
02:14 mareko: DemiMarie: if you use compute and 64x1 workgroups (linear access pattern), it should be fast, or glBlitFramebuffer/glCopyImageSubData if the driver implements it that way
02:14 DemiMarie: Is fuzzing compositors and UMDs the best option?
02:15 DemiMarie: mareko: Nice!
02:16 DemiMarie: The problem I am dealing with is making sure that the compositor won’t read out of bounds when passed maliciously crafted buffers.
02:17 DemiMarie: For linear buffers this is trivial, except for alignment. For nonlinear buffers it seems that the best I can do is hardware-in-the-loop fuzzing of thousands of lines of Mesa code.
04:31 DemiMarie: Does robustImageAccess2 typically check against the image size or dimensions? If it checks against the image size, then my concern is completely mitigated.
04:46 mareko: DemiMarie: it checks against the result of imageSize() in GLSL
04:47 mareko: there is never any out-of-bounds access if you don't use pointers in shaders
06:54 MrCooper: DemiMarie: buffer access is always bounded within height * stride, even with tiling; though note that the height needs to be aligned to a tile boundary
06:57 MrCooper: zamundaaa[m]: I'd have to see the code, FWIW adjusting the source & destination coordinates of the blit works in xf86-video-amdgpu/ati though
07:00 emersion: maybe glCopyTexSubImage would help
09:45 jani: straightforward review, anyone? https://lore.kernel.org/r/20240812122312.1567046-1-jani.nikula@intel.com
10:22 zamundaaa[m]: MrCooper: hmm, this code binds the buffer from the iGPU as a texture and uses that to render to the buffer on the dGPU. I haven't actually tried blitting
10:46 MrCooper: zamundaaa[m]: FWIW, "blits" are really textured quads with glamor in xserver
16:47 DemiMarie: MrCooper: if a tile is X bytes, are offset and stride required to be a multiple of X bytes?
16:48 DemiMarie: MrCooper: also, if I have a bunch of questions on modifiers, what is the best time to ask them?
16:49 MrCooper: the size of the buffer area which may be accessed is a multiple of the tile size, the stride not necessarily though
16:50 MrCooper: as always on IRC, just ask anytime, don't expect an immediate answer though
16:53 MrCooper: DemiMarie: the common definition of stride with tiling is a multiple of the tile width (>= the image width) multiplied by bytes per pixel
16:55 DemiMarie: MrCooper: is there a way to get the tile width from a dmabuf?
16:57 DemiMarie: MrCooper: can I assume that if client-provided stride is not an integer multiple of the bytes per pixel, the client is buggy?
16:59 DemiMarie: The reason I asked about time is that IRC doesn't have message history built in, and I wasn't sure if a question asked when people are offline would be seen later.
17:00 DemiMarie: Also, can I assume that if the format is subsampled, the width and height will be multiples of the subsampling ratio? That seems to be implied by the Vulkan valid usage requirements.
17:07 MrCooper: DemiMarie: not that I know of, the tile width is part of the modifier definition
17:08 DemiMarie: MrCooper: will the offset always be a multiple of it?
17:08 MrCooper: don't think it necessarily has to be
17:10 DemiMarie: Does that mean that for a given format and modifier, I can compute the minimum buffer size without knowing the hardware?
18:01 agd5f: modifiers only relay the layout, not alignment requirements
18:03 DemiMarie: Is that because the alignment requirements are always computable from the modifier and format for a given hardware model and generation?
20:30 agd5f: Not sure about alignment requirements within a GPU vendor. I would assume they should be compatible, but modifiers don't require that as far as I know. In general alignment requirements tend to be complex so it was a hard problem to solve.
23:22 tarceri: py311-generator: FAIL code 1 (38.19=setup[5.43]+cmd[32.76] seconds)
23:22 tarceri: https://gitlab.freedesktop.org/mesa/piglit/-/jobs/62520455
23:22 tarceri: Anyone know whats going on in these jobs with piglit?
23:23 tarceri: https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/944