05:11 Lynne: does the restrict qualifier do anything these days with vulkan?
05:11 Lynne: is there even a mapping for it under spir-v?
07:12 showingsomeform: So the data access works in mysterious way, first you get the 2times the value, by using such arithmetic 883+115=998 1024-998=26 888+120=1008 1024-1008=16 //443−89-256=98 840−115−115−512=98 838-120-120-512=86 120-16=104 115-26=89 190-104=86 187-89=98 , so you can get two times 98-26=72 or 86-16=70 or 66 or 69, then you reindex them, by adding base and index, it's for caching simpler
07:12 showingsomeform: to add same indexes as from first selection, and then to avoid division by two, there will be a table based of what to eliminate, so 883 is 115+768, you separate 446+442 and 443+446 and 443+440 triplets and table is filled in 1024-446-442-115=B 1024-443-446-115=C 1024-443-440-115=A so same thing but 120 replaced you get Y Z X and we mark 26 as D 16 as F, so 115 as BCAi and 120 as
07:12 showingsomeform: YZXi, we have two more terms 889.00−115−256−512=6 889.00=446+443-120−256−512=1, call them BCAd and YZXd d=delta, now value at 115 is YZXv=BCAi-C+BCAd-D =115-20+1-26=96-26=70 and BCAv=YZXi-F-YZXd-D=120-26-6-16=88-16=72 , notice how things get swapped, this table has proven to work, cause division by two has to change the format otherwise, we avoid that with such mechanism based table.
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12:30 alyssa: Lynne: in theory...
14:05 Lynne: I know what happened, someone was relying on this back in 1999 so rather than make restrict the default, they had no choice
14:28 Lynne: any way to debug "The CS has been rejected, see dmesg for more information"?
14:29 Lynne: validation layers empty, dmesg empty, valgrind clean
14:36 zmike: usually you fucked up descriptors
14:58 Lynne: not even any descriptors, just a single pipeline barrier in the cs
15:52 zmike: dj-death: I think I'll need your ack on https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31590
18:31 mlankhorst: can I force forward my gitlab tree to drm-tip without actually uploading all of drm-tip history?
18:50 dschuermann: do I really need a matrix account in order to participate in xdc chat?
18:57 emersion: :(
19:39 Gess1t: Hey, i'm currently having some issues running zinc on my raspberry 4, on any versions above the latest on oldstable bullseye (20.3.5), i would need need some help in troubleshooting it & fixing it if possible
19:42 Gess1t: I compiled a couple versions, including the latest release tag, a couple days ago (24.2.4), however, they all error out with these lines when running an app with zinc:
19:42 Gess1t: WARNING: v3dv is neither a complete nor a conformant Vulkan implementation. Testing use only.glx: failed to create drisw screenfailed to load driver: zinkdid not find extension DRI_CopySubBuffer version 1
19:42 Gess1t: these are repeated 20 times before a segfault happen.
19:43 Gess1t: as for the command used, here it is; using the compiled & locally installed binaries
19:43 Gess1t: LD_LIBRARY_PATH=/usr/local/lib/aarch64-linux-gnu LIBGL_DRIVERS_PATH=/usr/local/lib/aarch64-linux-gnu/dri MESA_GL_VERSION_OVERRIDE=3.2 MESA_GLSL_VERSION_OVERRIDE=320 __GLX_VENDOR_LIBRARY_NAME=mesa MESA_LOADER_DRIVER_OVERRIDE=zink LIBGL_DEBUG=verbose ZINK_DEBUG=verbose MESA_DEBUG=1 glxinfo -B
19:44 Gess1t: What i assume i need to do, is compiling some other libraries, but which is the question here
20:47 frizamite: I am aware of probably nearly all possibilities that i won't be typing over to here. So there is also one shortcut where two different indexes are aggregated together, with neglible or subtantially higher storage cost, this one also avoids division by two. But as for compute engine of course i am pretty sure alike, because i worked in cambodia not as gangstalker but flattening netlists of
20:47 frizamite: buses , gpus , cpus , signal/clock generators with the help of solvers , checked their timing analysis, transistor interconnections, and i know everything needed about computer heart inner workings and design, the combinatory of powers follows the bus signals about deserialization format of weighted powers, and i am correct on my vision and mission, abortion leftovers who butchered me and
20:47 frizamite: told the world that they are big deals are just abortion leftovers from birth, they always were like you and they always will be abondened scum in world, and there are none to blame , they were born incapable cheats and narcissist handycaps, i have not victimized them despite the terror gotten, eventually they get cleaned out from streets and public places, i know russian feds that expand
20:47 frizamite: in europe with war strategy especially do not adore such absurd human trash.
21:12 dliviu: gfxstrand: hi, I've been pointed by robclark to a drm/uring project on freedesktop.org but I cannot see/access it. Can you please add me to the project?
21:43 marc2377: Hey, masters. Last time I was here I asked about openchrome drm and xf86-video-openchrome, in the context of an ancient laptop with Openchrome Pro. And it was suggested to me to use simpledrm (which I believe also requires simplefb to be enabled in the kernel). I was able to get X to work on it (Cinnamon and LightDM). Just to confirm - the way it works is through Gallium3d LLVMPipe, which is part of Mesa, right?
21:43 marc2377: Do I need xf86-video-fbdev installed or not?
21:49 Ermine: marc2377: afaik 1) llvmpipe is a part of mesa; 2) you don't need xf86-video-fbdev
21:59 Ermine: https://docs.kernel.org/gpu/drm-internals.html#c.drm_driver --- it says that default impl of dumb_map_offset is drm_gem_create_mmap_offset, but their signatures do not match
22:19 radiosum81: so Lynne: those are jokes I address your question, pointers are orthogonal to the subject you asked, all memory exposed to shader is from LDS or global memory hunks and behind mmu, their physical address is never available to the shader unless it is an interrupt or you expose MMIO PM4 and alike copy engines registers to the shader engine. (I talk in radeon terminology of GCN but other gpus
22:19 radiosum81: are just alike) So you have work-items in opencl and things can be private local or global. Now let's talk about the performance rants, volta vs ampere note is also just bullshit, gpu can be made to underperform only in software if it was not a joke silicon wafer. Now the highest fuck off to venitlator manufacturers is self-timing of cross domain checkings in the interconnect, but it is a
22:19 radiosum81: big killer to expose verbally to anyone one planet cause it would expose hypersonic weapon, though to a bigger expert like me it's still easy but i am not a killer though whished by some narcissists. Next off combined with something i work on small weighted powers compression and exectution combined it would be just no resistance on the circuit, and heat is product of resistance, now move
22:19 radiosum81: to maximum workgroups per thread, which is next highest optimization purely in hardware that has not been exposed due to safety alike. Then there is soft-clause plus mmio scheduling tweak for endless recursed execution in register files, and scheduling which is so easy concept with early z culling are pretty much the most bottom items with yeah considerable performance wins too. Now those
22:19 radiosum81: mindill trashes waste my time, but deserialization format is fixed and values have no meaning without arithmetic so from boolean combinations of 1024 to arrive all other states is that meaning of computation or other states comes into play with alu ops only exclusively. I understand that world , but not all do, cause my brain backs it up, and not everyones does. depthcull.cg in google
22:19 radiosum81: which is similar optimization provides some insights. now video decoders today are built by generators like dlvc, dunno about chatgpt.
22:22 Ermine: dwfreed: I beg you
22:22 dwfreed: Ermine: ack
22:23 Ermine: thank you
22:43 Ermine: Seems like docs should specify drm_gem_dumb_map_offset as default dumb_map_offset impl?
22:46 Ermine: (same goes for dumb_map_offset TODO list entry?)