02:52 Ermine: is there documentation on what do nir passes expect from callbacks they call?
07:34 glehmann: valentine: looks like collabora's adreno CI is having issues: https://gitlab.freedesktop.org/mesa/mesa/-/jobs/103947924
07:39 valentine: glehmann: should be fixed now, apologies
14:04 MrCooper: Venemo: https://gitlab.freedesktop.org/drm/amd/-/work_items/5432#note_3549493 is a bit sad; if something's unclear in my comments, feel free to ask, instead of just responding with false assertions like that
14:05 Venemo: MrCooper: wdym false assertions like what?
14:05 MrCooper: your comment contains 3 claims, all of which are false
14:05 Venemo: why do you think that?
14:06 MrCooper: see my comments, ask if something's unclear
14:06 Venemo: I just read your comments, it's unclear why you are saying what I said was fals
14:06 MrCooper: well because they are
14:06 Venemo: please elaborate
14:06 MrCooper: nothing personal, just a fact
14:07 MrCooper: I already elaborated in my comments
14:07 Venemo: you just said: if it's unclear I can ask. well it's unclear so please explain more
14:07 MrCooper: specific questions please
14:09 Venemo: do you prefer to discuss here or in the gitlab comments?
14:10 MrCooper: slight preference for the latter
14:10 Venemo: ok
21:44 shivamklr: Hey everyone,
21:48 shivamklr: It appears that I am getting ring resets on my sdma and vcn. While looking at the source code of the amd gpu, the case for spurious resets for these engines seem to be missing.
21:49 shivamklr: In the current state, the rings reset without checking for if the job i
21:50 shivamklr: is* complete or not.