09:19 wens: got some weird bounce error from dri-devel@: <dri-devel@lists.freedesktop.org>: mail for lists.freedesktop.org loops back to myself
10:29 jannau: are there panfrost g925 targets running vulkan cts? I haven't seen anything in the nightly CI run. I'm wondering whether dEQP-VK.wsi.xcb.present_timing.basic.timing_queue still fails? It doesn't anymore on asahi
10:38 austriancoder: jannau: https://gitlab.freedesktop.org/mesa/mesa/-/blob/main/src/panfrost/ci/panfrost-g925-fails.txt?ref_type=heads#L769
10:44 jannau: yes, that's why I'm asking. the question is whether it still fails
10:51 valentine: jannau: looks like that one's also listed in flakes, so that will be hiding whether it's failing or not
10:51 valentine: but otherwise g925 is pre-merge, which is why you didn't see it in the nightly
10:52 valentine: could be worth dropping the flake and checking the job afterwards
10:54 jannau: I'm bisecting right now. if it's pre-merge I'll just update the panfrost files as well and look at the results
13:40 FireBurn: I think I have a fully working vino :D If anyone has a Dell D6000 feel free to give it a spin https://gitlab.freedesktop.org/FireBurn/linux/-/commits/vino
13:41 FireBurn: I'm gonna try and improve the efficany at 120Hz then clean it all up
14:40 mlankhorst: Would be nice if we could do a vm-bind style api for modesetting, having all buffers pre-pinned
15:39 FireBurn: I'll see what I can do
19:55 robclark: mupuf: does a750/ci-tron not mount debugfs? init_stage2 debugfs write fail: https://gitlab.freedesktop.org/mesa/mesa/-/jobs/106020756#L2208
20:59 Sachiel: glehmann: rounding mode per instruction is not something nir does or we care to make it do, right?
20:59 Sachiel: karolherbst: maybe CL has something to say about that? ^
21:00 glehmann: Sachiel: in general, no, nir doesn't do that. We have a few opcodes that use specific rounding like f2f16_rtz though
21:00 glehmann: so the real question is: why are you asking and what are you trying to do?
21:02 Sachiel: the RoundEven with RTZ set in the execution mode thing. We are using the lower_round_even from nir_lower_double_ops, and I'm wondering if I need to move that to the backend and suffer with the 64 bit handling or if there's a sane way to fix that pass
21:04 glehmann: ah I guess that's my fault because I asked for cts :D
21:04 glehmann: one solution would be to add a nir_op_fadd_rtne opcode
21:05 Sachiel: it is looking like the saner choice, thanks
21:11 karolherbst: Sachiel: the only per instruction rounding mode CL has are in conversions
21:11 karolherbst: there was a pragma that worked per instruction in 1.0 but it got deprecated/remove
21:11 karolherbst: d
21:13 Sachiel: alright, thanks