00:05 FireBurn: That's the vino driver cleaned up a lot
03:43 mupuf: robclark: No, we do not mount debugfs by default in boot2container, I guess this would be a difference with what stage1 of mesa ci does?
03:43 mupuf:takes a look
03:45 mupuf: yeah, this is part of stage1. I guess we should move it to stage2.
14:34 karolherbst: I'm looking at `pipe_context::memory_barrier` again and I'm kinda wondering what's the actual definition of it? Does it need to be called when the CPU writes to memory via maps? Or also when the GPU writes to it? I thought it's just the former mostly?
14:35 karolherbst: I guess that's mostly GLs memorybarrier?
14:37 zmike: it depends on the flags passed
14:38 karolherbst: okay.. I guess if a shader writes to an SSBO that is then later used as a UBO needs memory_barrier(PIPE_BARRIER_CONSTANT_BUFFER)
14:39 zmike: I usually just look at barrier.c whenever I need to remember how it's supposed to work
14:39 karolherbst: or if a shader writes to an image that is later used as a texture would require PIPE_BARRIER_TEXTURE
14:40 karolherbst: yeah.. I'm kinda wondering e.g. if a shader writes to an image and a later shader reads from that image, no barrier would be needed, right?
14:41 karolherbst: or would that require a barrier?
14:41 zmike: if it's the same shader in the same draw/dispatch then the shader needs to do appropriate synchronization
14:41 zmike: otherwise it requires a memory_barrier call
14:42 karolherbst: right..
14:42 karolherbst: it sucks because in CL those things are all kinda implicitly handled by the runtime and I kinda cheaped out on it so far...
14:46 zmike: you could just insert a compute barrier between every dispatch
14:46 zmike: for an in-order execution queue
14:46 zmike: for out-of-order queue you would need to be inserting memory barriers anyway
14:48 karolherbst: yeah....
14:48 karolherbst: but I'm also not flushing between every dispatch anymore
14:48 karolherbst: so drivers could run those out of order anyway
14:48 karolherbst: maybe
14:48 karolherbst: I don't know actually 🙃
14:48 zmike: they could, yes
14:48 karolherbst: right.. so I'd need to barrier them
14:49 zmike: yes
14:49 karolherbst: I had fun with this on nvidia, because the hw even runs compute dispatches out of order from the command buffer, a lot of fun
14:49 zmike: that's how a lot of hw works
14:51 karolherbst: what do you mean by compute barrier though?
14:52 zmike: realistically you'd just do PIPE_BARRIER_ALL
14:53 karolherbst: right...
21:55 Sachiel: zmike: any reason zink uses nir_lower_dround_even instead of just passing it as is and letting the driver below handle it?
22:02 zmike: pretty sure that came from someone else
22:03 zmike: I don't know why it is used
22:04 Sachiel: oh, moved to nir from the glsl compiler
22:04 Sachiel: guess I should look into just passing that forward