Status: fail
Result: fail
Detail | Value |
---|---|
returncode | 1 |
time | 0.0998950004578 |
note | Returncode was 1 |
command | /home/daenzer/src/piglit-git/piglit/framework/../bin/glsl-vs-loop-nested -auto |
errors_ignored |
|
errors |
|
info | Returncode: 1 Errors: LLVM ERROR: Cannot select: 0x1f43f20: i32 = sra 0x1f43e20, 0x1f36730 [ID=144] 0x1f43e20: i32 = add 0x1f42610, 0x1f43d20 [ID=138] 0x1f42610: i32 = fp_to_sint 0x1f37e50 [ORD=97] [ID=108] 0x1f37e50: f32 = extract_vector_elt 0x1f37130, 0x1f36a30 [ORD=20] [ID=88] 0x1f37130: v4f32,ch = llvm.SI.vs.load.input 0x1f37030, 0x1f33ad0, 0x1f36f30, 0x1f33bd0, 0x1f44d30 [ORD=16] [ID=71] 0x1f33ad0: i64 = TargetConstant<2659> [ORD=7] [ID=5] 0x1f36f30: v4i32,ch = load 0x1f33cd0:1, 0x1f36e30, 0x1f334d0<LD16[%10]> [ORD=14] [ID=65] 0x1f36e30: i64 = add 0x1f44c30, 0x1f36d30 [ORD=13] [ID=61] 0x1f44c30: i64 = Register %vreg36 [ID=41] 0x1f36d30: i64 = Constant<16> [ORD=13] [ID=10] 0x1f334d0: i64 = undef [ORD=3] [ID=4] 0x1f33bd0: i32 = Constant<0> [ORD=7] [ID=6] 0x1f44d30: i32 = Register %vreg37 [ID=42] 0x1f36a30: i64 = Constant<3> [ORD=11] [ID=9] 0x1f43d20: i32 = srl 0x1f43010, 0x1f43110 [ID=133] 0x1f43010: i32 = sra 0x1f42610, 0x1f42d10 [ID=128] 0x1f42610: i32 = fp_to_sint 0x1f37e50 [ORD=97] [ID=108] 0x1f37e50: f32 = extract_vector_elt 0x1f37130, 0x1f36a30 [ORD=20] [ID=88] 0x1f37130: v4f32,ch = llvm.SI.vs.load.input 0x1f37030, 0x1f33ad0, 0x1f36f30, 0x1f33bd0, 0x1f44d30 [ORD=16] [ID=71] 0x1f33ad0: i64 = TargetConstant<2659> [ORD=7] [ID=5] 0x1f36f30: v4i32,ch = load 0x1f33cd0:1, 0x1f36e30, 0x1f334d0<LD16[%10]> [ORD=14] [ID=65] 0x1f36e30: i64 = add 0x1f44c30, 0x1f36d30 [ORD=13] [ID=61] 0x1f44c30: i64 = Register %vreg36 [ID=41] 0x1f36d30: i64 = Constant<16> [ORD=13] [ID=10] 0x1f334d0: i64 = undef [ORD=3] [ID=4] 0x1f33bd0: i32 = Constant<0> [ORD=7] [ID=6] 0x1f44d30: i32 = Register %vreg37 [ID=42] 0x1f36a30: i64 = Constant<3> [ORD=11] [ID=9] 0x1f42d10: i64 = Constant<31> [ID=37] 0x1f43110: i64 = Constant<30> [ID=38] 0x1f36730: i64 = Constant<2> [ORD=10] [ID=8] In function: main Output: |