Status: fail
Result: fail
| Detail | Value |
|---|---|
| returncode | 1 |
| time | 0.105675935745 |
| note | Returncode was 1 |
| command | /home/daenzer/src/piglit-git/piglit/framework/../bin/ext_framebuffer_multisample-interpolation 0 centroid-deriv -auto |
| errors_ignored |
|
| errors |
|
| info | Returncode: 1
Errors:
warning: failed to translate tgsi opcode DDX to LLVM
Failed to translate shader from TGSI to LLVM
EE ../../../../../src/gallium/drivers/radeonsi/si_state.c:1907 si_shader_select - Failed to build shader variant (type=1) -22
LLVM ERROR: Cannot select: 0x1ddb7d0: i32 = truncate 0x1dd98b0 [ID=165]
0x1dd98b0: i64 = srl 0x1ddb6d0, 0x1dcf8c0 [ID=164]
0x1ddb6d0: i64 = mul 0x1ddaac0, 0x1ddb4d0 [ID=163]
0x1ddaac0: i64 = zero_extend 0x1ddb5d0 [ID=162]
0x1ddb5d0: i32 = select 0x1dda3c0, 0x1dd9fc0, 0x1dda0c0 [ID=160]
0x1dda3c0: i1 = setcc 0x1dde020, 0x1dc6c20, 0x1dd9bb0 [ID=141]
0x1dde020: i32 = truncate 0x1ddbdd0 [ID=139]
0x1ddbdd0: i64 = srl 0x1ddbcd0, 0x1dcf8c0 [ID=137]
0x1ddbcd0: i64 = mul 0x1ddb8d0, 0x1dd9db0 [ID=134]
0x1ddb8d0: i64 = zero_extend 0x1dcbc80 [ID=131]
0x1dd9db0: i64 = zero_extend 0x1dc9a60 [ID=126]
0x1dcf8c0: i64 = Constant<32> [ORD=108] [ID=16]
0x1dc6c20: i32 = Constant<0> [ORD=7] [ID=6]
0x1dd9fc0: i32 = add 0x1dcbc80, 0x1ddbbd0 [ID=157]
0x1dcbc80: i32 = URECIP 0x1dc9a60 [ID=127]
0x1dc9a60: i32 = xor 0x1dc9860, 0x1dc9660 [ID=119]
0x1dc9860: i32 = add 0x1dcbf80, 0x1dc9660 [ID=114]
0x1dcbf80: i32,ch = load 0x1dc6d20:1, 0x1dcb1b0, 0x1dc6520<LD4[%85]> [ID=80]
0x1dc9660: i32 = sra 0x1dcbf80, 0x1dd99b0 [ID=103]
0x1dc9660: i32 = sra 0x1dcbf80, 0x1dd99b0 [ID=103]
0x1dcbf80: i32,ch = load 0x1dc6d20:1, 0x1dcb1b0, 0x1dc6520<LD4[%85]> [ID=80]
0x1dd99b0: i64 = Constant<31> [ID=41]
0x1ddbbd0: i32 = truncate 0x1ddbad0 [ID=151]
0x1ddbad0: i64 = srl 0x1ddb9d0, 0x1dcf8c0 [ID=149]
0x1ddb9d0: i64 = mul 0x1dda2c0, 0x1ddb8d0 [ID=147]
0x1dda2c0: i64 = zero_extend 0x1dda1c0 [ID=145]
0x1ddb8d0: i64 = zero_extend 0x1dcbc80 [ID=131]
0x1dcf8c0: i64 = Constant<32> [ORD=108] [ID=16]
0x1dda0c0: i32 = sub 0x1dcbc80, 0x1ddbbd0 [ID=158]
0x1dcbc80: i32 = URECIP 0x1dc9a60 [ID=127]
0x1dc9a60: i32 = xor 0x1dc9860, 0x1dc9660 [ID=119]
0x1dc9860: i32 = add 0x1dcbf80, 0x1dc9660 [ID=114]
0x1dcbf80: i32,ch = load 0x1dc6d20:1, 0x1dcb1b0, 0x1dc6520<LD4[%85]> [ID=80]
0x1dc9660: i32 = sra 0x1dcbf80, 0x1dd99b0 [ID=103]
0x1dc9660: i32 = sra 0x1dcbf80, 0x1dd99b0 [ID=103]
0x1dcbf80: i32,ch = load 0x1dc6d20:1, 0x1dcb1b0, 0x1dc6520<LD4[%85]> [ID=80]
0x1dd99b0: i64 = Constant<31> [ID=41]
0x1ddbbd0: i32 = truncate 0x1ddbad0 [ID=151]
0x1ddbad0: i64 = srl 0x1ddb9d0, 0x1dcf8c0 [ID=149]
0x1ddb9d0: i64 = mul 0x1dda2c0, 0x1ddb8d0 [ID=147]
0x1dda2c0: i64 = zero_extend 0x1dda1c0 [ID=145]
0x1ddb8d0: i64 = zero_extend 0x1dcbc80 [ID=131]
0x1dcf8c0: i64 = Constant<32> [ORD=108] [ID=16]
0x1ddb4d0: i64 = zero_extend 0x1dc9960 [ID=121]
0x1dc9960: i32 = xor 0x1dc9760, 0x1dde120 [ID=116]
0x1dc9760: i32 = add 0x1dcc380, 0x1dde120 [ID=111]
0x1dcc380: i32,ch = load 0x1dc6d20:1, 0x1dca5b0, 0x1dc6520<LD4[%56]> [ID=79]
0x1dca5b0: i64 = add 0x1dd5720, 0x1dca4b0 [ORD=21] [ID=44]
0x1dd5720: i64 = Register %vreg0 [ID=35]
0x1dca4b0: i64 = Constant<16> [ORD=21] [ID=9]
0x1dc6520: i64 = undef [ORD=3] [ID=4]
0x1dde120: i32 = sra 0x1dcc380, 0x1dd99b0 [ID=100]
0x1dcc380: i32,ch = load 0x1dc6d20:1, 0x1dca5b0, 0x1dc6520<LD4[%56]> [ID=79]
0x1dca5b0: i64 = add 0x1dd5720, 0x1dca4b0 [ORD=21] [ID=44]
0x1dd5720: i64 = Register %vreg0 [ID=35]
0x1dca4b0: i64 = Constant<16> [ORD=21] [ID=9]
0x1dc6520: i64 = undef [ORD=3] [ID=4]
0x1dd99b0: i64 = Constant<31> [ID=41]
0x1dde120: i32 = sra 0x1dcc380, 0x1dd99b0 [ID=100]
0x1dcc380: i32,ch = load 0x1dc6d20:1, 0x1dca5b0, 0x1dc6520<LD4[%56]> [ID=79]
0x1dca5b0: i64 = add 0x1dd5720, 0x1dca4b0 [ORD=21] [ID=44]
0x1dd5720: i64 = Register %vreg0 [ID=35]
0x1dca4b0: i64 = Constant<16> [ORD=21] [ID=9]
0x1dc6520: i64 = undef [ORD=3] [ID=4]
0x1dd99b0: i64 = Constant<31> [ID=41]
0x1dcf8c0: i64 = Constant<32> [ORD=108] [ID=16]
In function: main
Output:
|