Status: fail
Result: fail
| Detail | Value |
|---|---|
| returncode | 1 |
| time | 0.112051010132 |
| note | Returncode was 1 |
| command | /home/daenzer/src/piglit-git/piglit/framework/../bin/ext_framebuffer_multisample-interpolation 0 centroid-deriv-disabled -auto |
| errors_ignored |
|
| errors |
|
| info | Returncode: 1
Errors:
warning: failed to translate tgsi opcode DDX to LLVM
Failed to translate shader from TGSI to LLVM
EE ../../../../../src/gallium/drivers/radeonsi/si_state.c:1907 si_shader_select - Failed to build shader variant (type=1) -22
LLVM ERROR: Cannot select: 0xfe6830: i32 = truncate 0xfe4910 [ID=165]
0xfe4910: i64 = srl 0xfe6730, 0xfda920 [ID=164]
0xfe6730: i64 = mul 0xfe5b20, 0xfe6530 [ID=163]
0xfe5b20: i64 = zero_extend 0xfe6630 [ID=162]
0xfe6630: i32 = select 0xfe5420, 0xfe5020, 0xfe5120 [ID=160]
0xfe5420: i1 = setcc 0xfe9080, 0xfd1c80, 0xfe4c10 [ID=141]
0xfe9080: i32 = truncate 0xfe6e30 [ID=139]
0xfe6e30: i64 = srl 0xfe6d30, 0xfda920 [ID=137]
0xfe6d30: i64 = mul 0xfe6930, 0xfe4e10 [ID=134]
0xfe6930: i64 = zero_extend 0xfd6ce0 [ID=131]
0xfe4e10: i64 = zero_extend 0xfd4ac0 [ID=126]
0xfda920: i64 = Constant<32> [ORD=108] [ID=16]
0xfd1c80: i32 = Constant<0> [ORD=7] [ID=6]
0xfe5020: i32 = add 0xfd6ce0, 0xfe6c30 [ID=157]
0xfd6ce0: i32 = URECIP 0xfd4ac0 [ID=127]
0xfd4ac0: i32 = xor 0xfd48c0, 0xfd46c0 [ID=119]
0xfd48c0: i32 = add 0xfd6fe0, 0xfd46c0 [ID=114]
0xfd6fe0: i32,ch = load 0xfd1d80:1, 0xfd6210, 0xfd1580<LD4[%85]> [ID=80]
0xfd46c0: i32 = sra 0xfd6fe0, 0xfe4a10 [ID=103]
0xfd46c0: i32 = sra 0xfd6fe0, 0xfe4a10 [ID=103]
0xfd6fe0: i32,ch = load 0xfd1d80:1, 0xfd6210, 0xfd1580<LD4[%85]> [ID=80]
0xfe4a10: i64 = Constant<31> [ID=41]
0xfe6c30: i32 = truncate 0xfe6b30 [ID=151]
0xfe6b30: i64 = srl 0xfe6a30, 0xfda920 [ID=149]
0xfe6a30: i64 = mul 0xfe5320, 0xfe6930 [ID=147]
0xfe5320: i64 = zero_extend 0xfe5220 [ID=145]
0xfe6930: i64 = zero_extend 0xfd6ce0 [ID=131]
0xfda920: i64 = Constant<32> [ORD=108] [ID=16]
0xfe5120: i32 = sub 0xfd6ce0, 0xfe6c30 [ID=158]
0xfd6ce0: i32 = URECIP 0xfd4ac0 [ID=127]
0xfd4ac0: i32 = xor 0xfd48c0, 0xfd46c0 [ID=119]
0xfd48c0: i32 = add 0xfd6fe0, 0xfd46c0 [ID=114]
0xfd6fe0: i32,ch = load 0xfd1d80:1, 0xfd6210, 0xfd1580<LD4[%85]> [ID=80]
0xfd46c0: i32 = sra 0xfd6fe0, 0xfe4a10 [ID=103]
0xfd46c0: i32 = sra 0xfd6fe0, 0xfe4a10 [ID=103]
0xfd6fe0: i32,ch = load 0xfd1d80:1, 0xfd6210, 0xfd1580<LD4[%85]> [ID=80]
0xfe4a10: i64 = Constant<31> [ID=41]
0xfe6c30: i32 = truncate 0xfe6b30 [ID=151]
0xfe6b30: i64 = srl 0xfe6a30, 0xfda920 [ID=149]
0xfe6a30: i64 = mul 0xfe5320, 0xfe6930 [ID=147]
0xfe5320: i64 = zero_extend 0xfe5220 [ID=145]
0xfe6930: i64 = zero_extend 0xfd6ce0 [ID=131]
0xfda920: i64 = Constant<32> [ORD=108] [ID=16]
0xfe6530: i64 = zero_extend 0xfd49c0 [ID=121]
0xfd49c0: i32 = xor 0xfd47c0, 0xfe9180 [ID=116]
0xfd47c0: i32 = add 0xfd73e0, 0xfe9180 [ID=111]
0xfd73e0: i32,ch = load 0xfd1d80:1, 0xfd5610, 0xfd1580<LD4[%56]> [ID=79]
0xfd5610: i64 = add 0xfe0780, 0xfd5510 [ORD=21] [ID=44]
0xfe0780: i64 = Register %vreg0 [ID=35]
0xfd5510: i64 = Constant<16> [ORD=21] [ID=9]
0xfd1580: i64 = undef [ORD=3] [ID=4]
0xfe9180: i32 = sra 0xfd73e0, 0xfe4a10 [ID=100]
0xfd73e0: i32,ch = load 0xfd1d80:1, 0xfd5610, 0xfd1580<LD4[%56]> [ID=79]
0xfd5610: i64 = add 0xfe0780, 0xfd5510 [ORD=21] [ID=44]
0xfe0780: i64 = Register %vreg0 [ID=35]
0xfd5510: i64 = Constant<16> [ORD=21] [ID=9]
0xfd1580: i64 = undef [ORD=3] [ID=4]
0xfe4a10: i64 = Constant<31> [ID=41]
0xfe9180: i32 = sra 0xfd73e0, 0xfe4a10 [ID=100]
0xfd73e0: i32,ch = load 0xfd1d80:1, 0xfd5610, 0xfd1580<LD4[%56]> [ID=79]
0xfd5610: i64 = add 0xfe0780, 0xfd5510 [ORD=21] [ID=44]
0xfe0780: i64 = Register %vreg0 [ID=35]
0xfd5510: i64 = Constant<16> [ORD=21] [ID=9]
0xfd1580: i64 = undef [ORD=3] [ID=4]
0xfe4a10: i64 = Constant<31> [ID=41]
0xfda920: i64 = Constant<32> [ORD=108] [ID=16]
In function: main
Output:
|