Results for spec/EXT_framebuffer_multisample/interpolation 0 non-centroid-deriv-disabled

Overview

Status: fail
Result: fail

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Details

Detail Value
returncode 1
time 0.108285903931
note
Returncode was 1
command
/home/daenzer/src/piglit-git/piglit/framework/../bin/ext_framebuffer_multisample-interpolation 0 non-centroid-deriv-disabled -auto
errors_ignored
  • 0x1765fa0: i32,ch = load 0x1760d40:1, 0x17651d0, 0x1760540<LD4[%85]> [ID=80]
  • 0x1765fa0: i32,ch = load 0x1760d40:1, 0x17651d0, 0x1760540<LD4[%85]> [ID=80]
  • 0x1765fa0: i32,ch = load 0x1760d40:1, 0x17651d0, 0x1760540<LD4[%85]> [ID=80]
  • 0x1765fa0: i32,ch = load 0x1760d40:1, 0x17651d0, 0x1760540<LD4[%85]> [ID=80]
  • 0x17663a0: i32,ch = load 0x1760d40:1, 0x17645d0, 0x1760540<LD4[%56]> [ID=79]
  • 0x176f740: i64 = Register %vreg0 [ID=35]
  • 0x17663a0: i32,ch = load 0x1760d40:1, 0x17645d0, 0x1760540<LD4[%56]> [ID=79]
  • 0x176f740: i64 = Register %vreg0 [ID=35]
  • 0x17663a0: i32,ch = load 0x1760d40:1, 0x17645d0, 0x1760540<LD4[%56]> [ID=79]
  • 0x176f740: i64 = Register %vreg0 [ID=35]
errors
  • warning: failed to translate tgsi opcode DDX to LLVM
  • Failed to translate shader from TGSI to LLVM
  • EE ../../../../../src/gallium/drivers/radeonsi/si_state.c:1907 si_shader_select - Failed to build shader variant (type=1) -22
  • LLVM ERROR: Cannot select: 0x17757f0: i32 = truncate 0x17738d0 [ID=165]
  • 0x17738d0: i64 = srl 0x17756f0, 0x17698e0 [ID=164]
  • 0x17756f0: i64 = mul 0x1774ae0, 0x17754f0 [ID=163]
  • 0x1774ae0: i64 = zero_extend 0x17755f0 [ID=162]
  • 0x17755f0: i32 = select 0x17743e0, 0x1773fe0, 0x17740e0 [ID=160]
  • 0x17743e0: i1 = setcc 0x1778040, 0x1760c40, 0x1773bd0 [ID=141]
  • 0x1778040: i32 = truncate 0x1775df0 [ID=139]
  • 0x1775df0: i64 = srl 0x1775cf0, 0x17698e0 [ID=137]
  • 0x1775cf0: i64 = mul 0x17758f0, 0x1773dd0 [ID=134]
  • 0x17758f0: i64 = zero_extend 0x1765ca0 [ID=131]
  • 0x1773dd0: i64 = zero_extend 0x1763a80 [ID=126]
  • 0x17698e0: i64 = Constant<32> [ORD=108] [ID=16]
  • 0x1760c40: i32 = Constant<0> [ORD=7] [ID=6]
  • 0x1773fe0: i32 = add 0x1765ca0, 0x1775bf0 [ID=157]
  • 0x1765ca0: i32 = URECIP 0x1763a80 [ID=127]
  • 0x1763a80: i32 = xor 0x1763880, 0x1763680 [ID=119]
  • 0x1763880: i32 = add 0x1765fa0, 0x1763680 [ID=114]
  • 0x1763680: i32 = sra 0x1765fa0, 0x17739d0 [ID=103]
  • 0x1763680: i32 = sra 0x1765fa0, 0x17739d0 [ID=103]
  • 0x17739d0: i64 = Constant<31> [ID=41]
  • 0x1775bf0: i32 = truncate 0x1775af0 [ID=151]
  • 0x1775af0: i64 = srl 0x17759f0, 0x17698e0 [ID=149]
  • 0x17759f0: i64 = mul 0x17742e0, 0x17758f0 [ID=147]
  • 0x17742e0: i64 = zero_extend 0x17741e0 [ID=145]
  • 0x17758f0: i64 = zero_extend 0x1765ca0 [ID=131]
  • 0x17698e0: i64 = Constant<32> [ORD=108] [ID=16]
  • 0x17740e0: i32 = sub 0x1765ca0, 0x1775bf0 [ID=158]
  • 0x1765ca0: i32 = URECIP 0x1763a80 [ID=127]
  • 0x1763a80: i32 = xor 0x1763880, 0x1763680 [ID=119]
  • 0x1763880: i32 = add 0x1765fa0, 0x1763680 [ID=114]
  • 0x1763680: i32 = sra 0x1765fa0, 0x17739d0 [ID=103]
  • 0x1763680: i32 = sra 0x1765fa0, 0x17739d0 [ID=103]
  • 0x17739d0: i64 = Constant<31> [ID=41]
  • 0x1775bf0: i32 = truncate 0x1775af0 [ID=151]
  • 0x1775af0: i64 = srl 0x17759f0, 0x17698e0 [ID=149]
  • 0x17759f0: i64 = mul 0x17742e0, 0x17758f0 [ID=147]
  • 0x17742e0: i64 = zero_extend 0x17741e0 [ID=145]
  • 0x17758f0: i64 = zero_extend 0x1765ca0 [ID=131]
  • 0x17698e0: i64 = Constant<32> [ORD=108] [ID=16]
  • 0x17754f0: i64 = zero_extend 0x1763980 [ID=121]
  • 0x1763980: i32 = xor 0x1763780, 0x1778140 [ID=116]
  • 0x1763780: i32 = add 0x17663a0, 0x1778140 [ID=111]
  • 0x17645d0: i64 = add 0x176f740, 0x17644d0 [ORD=21] [ID=44]
  • 0x17644d0: i64 = Constant<16> [ORD=21] [ID=9]
  • 0x1760540: i64 = undef [ORD=3] [ID=4]
  • 0x1778140: i32 = sra 0x17663a0, 0x17739d0 [ID=100]
  • 0x17645d0: i64 = add 0x176f740, 0x17644d0 [ORD=21] [ID=44]
  • 0x17644d0: i64 = Constant<16> [ORD=21] [ID=9]
  • 0x1760540: i64 = undef [ORD=3] [ID=4]
  • 0x17739d0: i64 = Constant<31> [ID=41]
  • 0x1778140: i32 = sra 0x17663a0, 0x17739d0 [ID=100]
  • 0x17645d0: i64 = add 0x176f740, 0x17644d0 [ORD=21] [ID=44]
  • 0x17644d0: i64 = Constant<16> [ORD=21] [ID=9]
  • 0x1760540: i64 = undef [ORD=3] [ID=4]
  • 0x17739d0: i64 = Constant<31> [ID=41]
  • 0x17698e0: i64 = Constant<32> [ORD=108] [ID=16]
  • In function: main
info
Returncode: 1

Errors:
warning: failed to translate tgsi opcode DDX to LLVM
Failed to translate shader from TGSI to LLVM
EE ../../../../../src/gallium/drivers/radeonsi/si_state.c:1907 si_shader_select - Failed to build shader variant (type=1) -22
LLVM ERROR: Cannot select: 0x17757f0: i32 = truncate 0x17738d0 [ID=165]
  0x17738d0: i64 = srl 0x17756f0, 0x17698e0 [ID=164]
    0x17756f0: i64 = mul 0x1774ae0, 0x17754f0 [ID=163]
      0x1774ae0: i64 = zero_extend 0x17755f0 [ID=162]
        0x17755f0: i32 = select 0x17743e0, 0x1773fe0, 0x17740e0 [ID=160]
          0x17743e0: i1 = setcc 0x1778040, 0x1760c40, 0x1773bd0 [ID=141]
            0x1778040: i32 = truncate 0x1775df0 [ID=139]
              0x1775df0: i64 = srl 0x1775cf0, 0x17698e0 [ID=137]
                0x1775cf0: i64 = mul 0x17758f0, 0x1773dd0 [ID=134]
                  0x17758f0: i64 = zero_extend 0x1765ca0 [ID=131]

                  0x1773dd0: i64 = zero_extend 0x1763a80 [ID=126]

                0x17698e0: i64 = Constant<32> [ORD=108] [ID=16]
            0x1760c40: i32 = Constant<0> [ORD=7] [ID=6]
          0x1773fe0: i32 = add 0x1765ca0, 0x1775bf0 [ID=157]
            0x1765ca0: i32 = URECIP 0x1763a80 [ID=127]
              0x1763a80: i32 = xor 0x1763880, 0x1763680 [ID=119]
                0x1763880: i32 = add 0x1765fa0, 0x1763680 [ID=114]
                  0x1765fa0: i32,ch = load 0x1760d40:1, 0x17651d0, 0x1760540<LD4[%85]> [ID=80]


                  0x1763680: i32 = sra 0x1765fa0, 0x17739d0 [ID=103]


                0x1763680: i32 = sra 0x1765fa0, 0x17739d0 [ID=103]
                  0x1765fa0: i32,ch = load 0x1760d40:1, 0x17651d0, 0x1760540<LD4[%85]> [ID=80]


                  0x17739d0: i64 = Constant<31> [ID=41]
            0x1775bf0: i32 = truncate 0x1775af0 [ID=151]
              0x1775af0: i64 = srl 0x17759f0, 0x17698e0 [ID=149]
                0x17759f0: i64 = mul 0x17742e0, 0x17758f0 [ID=147]
                  0x17742e0: i64 = zero_extend 0x17741e0 [ID=145]

                  0x17758f0: i64 = zero_extend 0x1765ca0 [ID=131]

                0x17698e0: i64 = Constant<32> [ORD=108] [ID=16]
          0x17740e0: i32 = sub 0x1765ca0, 0x1775bf0 [ID=158]
            0x1765ca0: i32 = URECIP 0x1763a80 [ID=127]
              0x1763a80: i32 = xor 0x1763880, 0x1763680 [ID=119]
                0x1763880: i32 = add 0x1765fa0, 0x1763680 [ID=114]
                  0x1765fa0: i32,ch = load 0x1760d40:1, 0x17651d0, 0x1760540<LD4[%85]> [ID=80]


                  0x1763680: i32 = sra 0x1765fa0, 0x17739d0 [ID=103]


                0x1763680: i32 = sra 0x1765fa0, 0x17739d0 [ID=103]
                  0x1765fa0: i32,ch = load 0x1760d40:1, 0x17651d0, 0x1760540<LD4[%85]> [ID=80]


                  0x17739d0: i64 = Constant<31> [ID=41]
            0x1775bf0: i32 = truncate 0x1775af0 [ID=151]
              0x1775af0: i64 = srl 0x17759f0, 0x17698e0 [ID=149]
                0x17759f0: i64 = mul 0x17742e0, 0x17758f0 [ID=147]
                  0x17742e0: i64 = zero_extend 0x17741e0 [ID=145]

                  0x17758f0: i64 = zero_extend 0x1765ca0 [ID=131]

                0x17698e0: i64 = Constant<32> [ORD=108] [ID=16]
      0x17754f0: i64 = zero_extend 0x1763980 [ID=121]
        0x1763980: i32 = xor 0x1763780, 0x1778140 [ID=116]
          0x1763780: i32 = add 0x17663a0, 0x1778140 [ID=111]
            0x17663a0: i32,ch = load 0x1760d40:1, 0x17645d0, 0x1760540<LD4[%56]> [ID=79]
              0x17645d0: i64 = add 0x176f740, 0x17644d0 [ORD=21] [ID=44]
                0x176f740: i64 = Register %vreg0 [ID=35]
                0x17644d0: i64 = Constant<16> [ORD=21] [ID=9]
              0x1760540: i64 = undef [ORD=3] [ID=4]
            0x1778140: i32 = sra 0x17663a0, 0x17739d0 [ID=100]
              0x17663a0: i32,ch = load 0x1760d40:1, 0x17645d0, 0x1760540<LD4[%56]> [ID=79]
                0x17645d0: i64 = add 0x176f740, 0x17644d0 [ORD=21] [ID=44]
                  0x176f740: i64 = Register %vreg0 [ID=35]
                  0x17644d0: i64 = Constant<16> [ORD=21] [ID=9]
                0x1760540: i64 = undef [ORD=3] [ID=4]
              0x17739d0: i64 = Constant<31> [ID=41]
          0x1778140: i32 = sra 0x17663a0, 0x17739d0 [ID=100]
            0x17663a0: i32,ch = load 0x1760d40:1, 0x17645d0, 0x1760540<LD4[%56]> [ID=79]
              0x17645d0: i64 = add 0x176f740, 0x17644d0 [ORD=21] [ID=44]
                0x176f740: i64 = Register %vreg0 [ID=35]
                0x17644d0: i64 = Constant<16> [ORD=21] [ID=9]
              0x1760540: i64 = undef [ORD=3] [ID=4]
            0x17739d0: i64 = Constant<31> [ID=41]
    0x17698e0: i64 = Constant<32> [ORD=108] [ID=16]
In function: main


Output:

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