Status: fail
Result: fail
| Detail | Value |
|---|---|
| returncode | 1 |
| time | 0.101629018784 |
| note | Returncode was 1 |
| command | /home/daenzer/src/piglit-git/piglit/framework/../bin/shader_runner tests/../generated_tests/spec/glsl-1.10/execution/built-in-functions/fs-op-div-int-int.shader_test -auto |
| errors_ignored |
|
| errors |
|
| info | Returncode: 1
Errors:
LLVM ERROR: Cannot select: 0x1cd3d20: i32 = truncate 0x1cd1e70 [ID=56]
0x1cd1e70: i64 = srl 0x1cd3c20, 0x1ccc250 [ID=55]
0x1cd3c20: i64 = mul 0x1cd3120, 0x1cd3a20 [ID=54]
0x1cd3120: i64 = zero_extend 0x1cd3b20 [ID=53]
0x1cd3b20: i32 = select 0x1cd2770, 0x1cd2370, 0x1cd2470 [ID=52]
0x1cd2770: i1 = setcc 0x1cd4940, 0x1ccbd50, 0x1ccf1f0 [ID=44]
0x1cd4940: i32 = truncate 0x1cd4840 [ID=43]
0x1cd4840: i64 = srl 0x1cd4740, 0x1ccc250 [ID=42]
0x1cd4740: i64 = mul 0x1cd4340, 0x1cd2270 [ID=40]
0x1cd4340: i64 = zero_extend 0x1ccc550 [ID=38]
0x1cd2270: i64 = zero_extend 0x1ccf4f0 [ID=36]
0x1ccc250: i64 = Constant<32> [ORD=3] [ID=4]
0x1ccbd50: i32 = Constant<0> [ORD=1] [ID=2]
0x1cd2370: i32 = add 0x1ccc550, 0x1cd4640 [ID=50]
0x1ccc550: i32 = URECIP 0x1ccf4f0 [ID=37]
0x1ccf4f0: i32 = xor 0x1ccf0f0, 0x1ccc450 [ID=34]
0x1ccf0f0: i32 = add 0x1cceef0, 0x1ccc450 [ID=32]
0x1cceef0: i32,ch = load 0x1ccbe50, 0x1ccc750, 0x1ccc050<LD4[%5]> [ID=25]
0x1ccc450: i32 = sra 0x1cceef0, 0x1cd1f70 [ID=28]
0x1ccc450: i32 = sra 0x1cceef0, 0x1cd1f70 [ID=28]
0x1cceef0: i32,ch = load 0x1ccbe50, 0x1ccc750, 0x1ccc050<LD4[%5]> [ID=25]
0x1cd1f70: i64 = Constant<31> [ID=17]
0x1cd4640: i32 = truncate 0x1cd4540 [ID=49]
0x1cd4540: i64 = srl 0x1cd4440, 0x1ccc250 [ID=48]
0x1cd4440: i64 = mul 0x1cd2670, 0x1cd4340 [ID=47]
0x1cd2670: i64 = zero_extend 0x1cd2570 [ID=46]
0x1cd4340: i64 = zero_extend 0x1ccc550 [ID=38]
0x1ccc250: i64 = Constant<32> [ORD=3] [ID=4]
0x1cd2470: i32 = sub 0x1ccc550, 0x1cd4640 [ID=51]
0x1ccc550: i32 = URECIP 0x1ccf4f0 [ID=37]
0x1ccf4f0: i32 = xor 0x1ccf0f0, 0x1ccc450 [ID=34]
0x1ccf0f0: i32 = add 0x1cceef0, 0x1ccc450 [ID=32]
0x1cceef0: i32,ch = load 0x1ccbe50, 0x1ccc750, 0x1ccc050<LD4[%5]> [ID=25]
0x1ccc450: i32 = sra 0x1cceef0, 0x1cd1f70 [ID=28]
0x1ccc450: i32 = sra 0x1cceef0, 0x1cd1f70 [ID=28]
0x1cceef0: i32,ch = load 0x1ccbe50, 0x1ccc750, 0x1ccc050<LD4[%5]> [ID=25]
0x1cd1f70: i64 = Constant<31> [ID=17]
0x1cd4640: i32 = truncate 0x1cd4540 [ID=49]
0x1cd4540: i64 = srl 0x1cd4440, 0x1ccc250 [ID=48]
0x1cd4440: i64 = mul 0x1cd2670, 0x1cd4340 [ID=47]
0x1cd2670: i64 = zero_extend 0x1cd2570 [ID=46]
0x1cd4340: i64 = zero_extend 0x1ccc550 [ID=38]
0x1ccc250: i64 = Constant<32> [ORD=3] [ID=4]
0x1cd3a20: i64 = zero_extend 0x1cceff0 [ID=35]
0x1cceff0: i32 = xor 0x1ccc850, 0x1cd4a40 [ID=33]
0x1ccc850: i32 = add 0x1ccf6f0, 0x1cd4a40 [ID=30]
0x1ccf6f0: i32,ch = load 0x1ccbe50, 0x1ccc350, 0x1ccc050<LD4[%1]> [ID=24]
0x1ccc350: i64 = add 0x1ccca50, 0x1ccc250 [ORD=3] [ID=21]
0x1ccca50: i64 = Register %vreg0 [ID=14]
0x1ccc250: i64 = Constant<32> [ORD=3] [ID=4]
0x1ccc050: i64 = undef [ORD=2] [ID=3]
0x1cd4a40: i32 = sra 0x1ccf6f0, 0x1cd1f70 [ID=26]
0x1ccf6f0: i32,ch = load 0x1ccbe50, 0x1ccc350, 0x1ccc050<LD4[%1]> [ID=24]
0x1ccc350: i64 = add 0x1ccca50, 0x1ccc250 [ORD=3] [ID=21]
0x1ccca50: i64 = Register %vreg0 [ID=14]
0x1ccc250: i64 = Constant<32> [ORD=3] [ID=4]
0x1ccc050: i64 = undef [ORD=2] [ID=3]
0x1cd1f70: i64 = Constant<31> [ID=17]
0x1cd4a40: i32 = sra 0x1ccf6f0, 0x1cd1f70 [ID=26]
0x1ccf6f0: i32,ch = load 0x1ccbe50, 0x1ccc350, 0x1ccc050<LD4[%1]> [ID=24]
0x1ccc350: i64 = add 0x1ccca50, 0x1ccc250 [ORD=3] [ID=21]
0x1ccca50: i64 = Register %vreg0 [ID=14]
0x1ccc250: i64 = Constant<32> [ORD=3] [ID=4]
0x1ccc050: i64 = undef [ORD=2] [ID=3]
0x1cd1f70: i64 = Constant<31> [ID=17]
0x1ccc250: i64 = Constant<32> [ORD=3] [ID=4]
In function: main
Output:
|