Results for spec/glsl-1.10/execution/built-in-functions/fs-op-ne-bvec2-bvec2

Overview

Status: fail
Result: fail

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Details

Detail Value
returncode 1
time 0.0798871517181
note 
Returncode was 1
command 
/home/daenzer/src/piglit-git/piglit/framework/../bin/shader_runner tests/../generated_tests/spec/glsl-1.10/execution/built-in-functions/fs-op-ne-bvec2-bvec2.shader_test -auto
errors_ignored 
  • 0x10ef050: i32,ch = load 0x10ebbf0, 0x10ec0f0, 0x10ebdf0<LD4[%1]> [ID=22]
  • 0x10ec4f0: i64 = Register %vreg0 [ID=15]
  • 0x10ef450: i32,ch = load 0x10ebbf0, 0x10ec4f0, 0x10ebdf0<LD4[%5]> [ID=21]
  • 0x10ec4f0: i64 = Register %vreg0 [ID=15]
  • 0x10f0bb0: i32,ch = load 0x10ebbf0, 0x10eee50, 0x10ebdf0<LD4[%11]> [ID=23]
  • 0x10ec4f0: i64 = Register %vreg0 [ID=15]
  • 0x10ef950: i32,ch = load 0x10ebbf0, 0x10ef250, 0x10ebdf0<LD4[%15]> [ID=24]
  • 0x10ec4f0: i64 = Register %vreg0 [ID=15]
errors 
  • LLVM ERROR: Cannot select: 0x10f04b0: i32 = sign_extend 0x10efa50 [ID=29]
  • 0x10efa50: i1 = or 0x10ec6f0, 0x10ef550 [ID=28]
  • 0x10ec6f0: i1 = setcc 0x10ef050, 0x10ef450, 0x10ec5f0 [ORD=10] [ID=25]
  • 0x10ec0f0: i64 = add 0x10ec4f0, 0x10ebff0 [ORD=3] [ID=18]
  • 0x10ebff0: i64 = Constant<16> [ORD=3] [ID=4]
  • 0x10ebdf0: i64 = undef [ORD=2] [ID=3]
  • 0x10ebdf0: i64 = undef [ORD=2] [ID=3]
  • 0x10ef550: i1 = setcc 0x10f0bb0, 0x10ef950, 0x10ec5f0 [ORD=20] [ID=26]
  • 0x10eee50: i64 = add 0x10ec4f0, 0x10eed50 [ORD=13] [ID=19]
  • 0x10eed50: i64 = Constant<20> [ORD=13] [ID=6]
  • 0x10ebdf0: i64 = undef [ORD=2] [ID=3]
  • 0x10ef250: i64 = add 0x10ec4f0, 0x10ef150 [ORD=17] [ID=20]
  • 0x10ef150: i64 = Constant<4> [ORD=17] [ID=7]
  • 0x10ebdf0: i64 = undef [ORD=2] [ID=3]
  • In function: main
info 
Returncode: 1

Errors:
LLVM ERROR: Cannot select: 0x10f04b0: i32 = sign_extend 0x10efa50 [ID=29]
  0x10efa50: i1 = or 0x10ec6f0, 0x10ef550 [ID=28]
    0x10ec6f0: i1 = setcc 0x10ef050, 0x10ef450, 0x10ec5f0 [ORD=10] [ID=25]
      0x10ef050: i32,ch = load 0x10ebbf0, 0x10ec0f0, 0x10ebdf0<LD4[%1]> [ID=22]
        0x10ec0f0: i64 = add 0x10ec4f0, 0x10ebff0 [ORD=3] [ID=18]
          0x10ec4f0: i64 = Register %vreg0 [ID=15]
          0x10ebff0: i64 = Constant<16> [ORD=3] [ID=4]
        0x10ebdf0: i64 = undef [ORD=2] [ID=3]
      0x10ef450: i32,ch = load 0x10ebbf0, 0x10ec4f0, 0x10ebdf0<LD4[%5]> [ID=21]
        0x10ec4f0: i64 = Register %vreg0 [ID=15]
        0x10ebdf0: i64 = undef [ORD=2] [ID=3]
    0x10ef550: i1 = setcc 0x10f0bb0, 0x10ef950, 0x10ec5f0 [ORD=20] [ID=26]
      0x10f0bb0: i32,ch = load 0x10ebbf0, 0x10eee50, 0x10ebdf0<LD4[%11]> [ID=23]
        0x10eee50: i64 = add 0x10ec4f0, 0x10eed50 [ORD=13] [ID=19]
          0x10ec4f0: i64 = Register %vreg0 [ID=15]
          0x10eed50: i64 = Constant<20> [ORD=13] [ID=6]
        0x10ebdf0: i64 = undef [ORD=2] [ID=3]
      0x10ef950: i32,ch = load 0x10ebbf0, 0x10ef250, 0x10ebdf0<LD4[%15]> [ID=24]
        0x10ef250: i64 = add 0x10ec4f0, 0x10ef150 [ORD=17] [ID=20]
          0x10ec4f0: i64 = Register %vreg0 [ID=15]
          0x10ef150: i64 = Constant<4> [ORD=17] [ID=7]
        0x10ebdf0: i64 = undef [ORD=2] [ID=3]
In function: main


Output:

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