Results for spec/glsl-1.10/execution/built-in-functions/fs-op-ne-bvec3-bvec3-using-if

Overview

Status: fail
Result: fail

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Details

Detail Value
returncode 1
time 0.09707903862
note 
Returncode was 1
command 
/home/daenzer/src/piglit-git/piglit/framework/../bin/shader_runner tests/../generated_tests/spec/glsl-1.10/execution/built-in-functions/fs-op-ne-bvec3-bvec3-using-if.shader_test -auto
errors_ignored 
  • 0x1d94c70: i32,ch = load 0x1d91810, 0x1d91d10, 0x1d91a10<LD4[%1]> [ID=25]
  • 0x1d96690: i64 = Register %vreg0 [ID=16]
  • 0x1d95070: i32,ch = load 0x1d91810, 0x1d96690, 0x1d91a10<LD4[%5]> [ID=24]
  • 0x1d96690: i64 = Register %vreg0 [ID=16]
  • 0x1d95670: i32,ch = load 0x1d91810, 0x1d94a70, 0x1d91a10<LD4[%11]> [ID=26]
  • 0x1d96690: i64 = Register %vreg0 [ID=16]
  • 0x1d95d90: i32,ch = load 0x1d91810, 0x1d94e70, 0x1d91a10<LD4[%15]> [ID=27]
  • 0x1d96690: i64 = Register %vreg0 [ID=16]
  • 0x1d96790: i32,ch = load 0x1d91810, 0x1d95470, 0x1d91a10<LD4[%21]> [ID=28]
  • 0x1d96690: i64 = Register %vreg0 [ID=16]
  • 0x1d971a0: i32,ch = load 0x1d91810, 0x1d95b90, 0x1d91a10<LD4[%25]> [ID=29]
  • 0x1d96690: i64 = Register %vreg0 [ID=16]
errors 
  • LLVM ERROR: Cannot select: 0x1d96390: i1 = or 0x1d92310, 0x1d96490 [ID=35]
  • 0x1d92310: i1 = setcc 0x1d94c70, 0x1d95070, 0x1d92210 [ORD=10] [ID=30]
  • 0x1d91d10: i64 = add 0x1d96690, 0x1d91c10 [ORD=3] [ID=19]
  • 0x1d91c10: i64 = Constant<16> [ORD=3] [ID=4]
  • 0x1d91a10: i64 = undef [ORD=2] [ID=3]
  • 0x1d91a10: i64 = undef [ORD=2] [ID=3]
  • 0x1d96490: i1 = or 0x1d95170, 0x1d95e90 [ID=34]
  • 0x1d95170: i1 = setcc 0x1d95670, 0x1d95d90, 0x1d92210 [ORD=20] [ID=31]
  • 0x1d94a70: i64 = add 0x1d96690, 0x1d94970 [ORD=13] [ID=20]
  • 0x1d94970: i64 = Constant<20> [ORD=13] [ID=6]
  • 0x1d91a10: i64 = undef [ORD=2] [ID=3]
  • 0x1d94e70: i64 = add 0x1d96690, 0x1d94d70 [ORD=17] [ID=21]
  • 0x1d94d70: i64 = Constant<4> [ORD=17] [ID=7]
  • 0x1d91a10: i64 = undef [ORD=2] [ID=3]
  • 0x1d95e90: i1 = setcc 0x1d96790, 0x1d971a0, 0x1d92210 [ORD=30] [ID=32]
  • 0x1d95470: i64 = add 0x1d96690, 0x1d95370 [ORD=23] [ID=22]
  • 0x1d95370: i64 = Constant<24> [ORD=23] [ID=8]
  • 0x1d91a10: i64 = undef [ORD=2] [ID=3]
  • 0x1d95b90: i64 = add 0x1d96690, 0x1d95770 [ORD=27] [ID=23]
  • 0x1d95770: i64 = Constant<8> [ORD=27] [ID=9]
  • 0x1d91a10: i64 = undef [ORD=2] [ID=3]
  • In function: main
info 
Returncode: 1

Errors:
LLVM ERROR: Cannot select: 0x1d96390: i1 = or 0x1d92310, 0x1d96490 [ID=35]
  0x1d92310: i1 = setcc 0x1d94c70, 0x1d95070, 0x1d92210 [ORD=10] [ID=30]
    0x1d94c70: i32,ch = load 0x1d91810, 0x1d91d10, 0x1d91a10<LD4[%1]> [ID=25]
      0x1d91d10: i64 = add 0x1d96690, 0x1d91c10 [ORD=3] [ID=19]
        0x1d96690: i64 = Register %vreg0 [ID=16]
        0x1d91c10: i64 = Constant<16> [ORD=3] [ID=4]
      0x1d91a10: i64 = undef [ORD=2] [ID=3]
    0x1d95070: i32,ch = load 0x1d91810, 0x1d96690, 0x1d91a10<LD4[%5]> [ID=24]
      0x1d96690: i64 = Register %vreg0 [ID=16]
      0x1d91a10: i64 = undef [ORD=2] [ID=3]
  0x1d96490: i1 = or 0x1d95170, 0x1d95e90 [ID=34]
    0x1d95170: i1 = setcc 0x1d95670, 0x1d95d90, 0x1d92210 [ORD=20] [ID=31]
      0x1d95670: i32,ch = load 0x1d91810, 0x1d94a70, 0x1d91a10<LD4[%11]> [ID=26]
        0x1d94a70: i64 = add 0x1d96690, 0x1d94970 [ORD=13] [ID=20]
          0x1d96690: i64 = Register %vreg0 [ID=16]
          0x1d94970: i64 = Constant<20> [ORD=13] [ID=6]
        0x1d91a10: i64 = undef [ORD=2] [ID=3]
      0x1d95d90: i32,ch = load 0x1d91810, 0x1d94e70, 0x1d91a10<LD4[%15]> [ID=27]
        0x1d94e70: i64 = add 0x1d96690, 0x1d94d70 [ORD=17] [ID=21]
          0x1d96690: i64 = Register %vreg0 [ID=16]
          0x1d94d70: i64 = Constant<4> [ORD=17] [ID=7]
        0x1d91a10: i64 = undef [ORD=2] [ID=3]
    0x1d95e90: i1 = setcc 0x1d96790, 0x1d971a0, 0x1d92210 [ORD=30] [ID=32]
      0x1d96790: i32,ch = load 0x1d91810, 0x1d95470, 0x1d91a10<LD4[%21]> [ID=28]
        0x1d95470: i64 = add 0x1d96690, 0x1d95370 [ORD=23] [ID=22]
          0x1d96690: i64 = Register %vreg0 [ID=16]
          0x1d95370: i64 = Constant<24> [ORD=23] [ID=8]
        0x1d91a10: i64 = undef [ORD=2] [ID=3]
      0x1d971a0: i32,ch = load 0x1d91810, 0x1d95b90, 0x1d91a10<LD4[%25]> [ID=29]
        0x1d95b90: i64 = add 0x1d96690, 0x1d95770 [ORD=27] [ID=23]
          0x1d96690: i64 = Register %vreg0 [ID=16]
          0x1d95770: i64 = Constant<8> [ORD=27] [ID=9]
        0x1d91a10: i64 = undef [ORD=2] [ID=3]
In function: main


Output:

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