Results for spec/glsl-1.10/execution/built-in-functions/fs-op-ne-ivec4-ivec4-using-if

Overview

Status: fail
Result: fail

Back to summary

Details

Detail Value
returncode 1
time 0.083233833313
note 
Returncode was 1
command 
/home/daenzer/src/piglit-git/piglit/framework/../bin/shader_runner tests/../generated_tests/spec/glsl-1.10/execution/built-in-functions/fs-op-ne-ivec4-ivec4-using-if.shader_test -auto
errors_ignored 
  • 0x1dbc420: i32,ch = load 0x1db8fc0, 0x1db94c0, 0x1db91c0<LD4[%1]> [ID=29]
  • 0x1dbe9f0: i64 = Register %vreg0 [ID=18]
  • 0x1dbc820: i32,ch = load 0x1db8fc0, 0x1dbe9f0, 0x1db91c0<LD4[%5]> [ID=28]
  • 0x1dbe9f0: i64 = Register %vreg0 [ID=18]
  • 0x1dbce20: i32,ch = load 0x1db8fc0, 0x1dbc220, 0x1db91c0<LD4[%11]> [ID=30]
  • 0x1dbe9f0: i64 = Register %vreg0 [ID=18]
  • 0x1dbd540: i32,ch = load 0x1db8fc0, 0x1dbc620, 0x1db91c0<LD4[%15]> [ID=31]
  • 0x1dbe9f0: i64 = Register %vreg0 [ID=18]
  • 0x1dbdb40: i32,ch = load 0x1db8fc0, 0x1dbcc20, 0x1db91c0<LD4[%21]> [ID=32]
  • 0x1dbe9f0: i64 = Register %vreg0 [ID=18]
  • 0x1dbdf40: i32,ch = load 0x1db8fc0, 0x1dbd340, 0x1db91c0<LD4[%25]> [ID=33]
  • 0x1dbe9f0: i64 = Register %vreg0 [ID=18]
  • 0x1dbedf0: i32,ch = load 0x1db8fc0, 0x1dbd940, 0x1db91c0<LD4[%31]> [ID=34]
  • 0x1dbe9f0: i64 = Register %vreg0 [ID=18]
  • 0x1dc0c20: i32,ch = load 0x1db8fc0, 0x1dbdd40, 0x1db91c0<LD4[%35]> [ID=35]
  • 0x1dbe9f0: i64 = Register %vreg0 [ID=18]
errors 
  • LLVM ERROR: Cannot select: 0x1dbe7f0: i1 = or 0x1dbe8f0, 0x1dbeaf0 [ID=43]
  • 0x1dbe8f0: i1 = or 0x1db9ac0, 0x1dbc920 [ID=41]
  • 0x1db9ac0: i1 = setcc 0x1dbc420, 0x1dbc820, 0x1db99c0 [ORD=10] [ID=36]
  • 0x1db94c0: i64 = add 0x1dbe9f0, 0x1db93c0 [ORD=3] [ID=21]
  • 0x1db93c0: i64 = Constant<16> [ORD=3] [ID=4]
  • 0x1db91c0: i64 = undef [ORD=2] [ID=3]
  • 0x1db91c0: i64 = undef [ORD=2] [ID=3]
  • 0x1dbc920: i1 = setcc 0x1dbce20, 0x1dbd540, 0x1db99c0 [ORD=20] [ID=37]
  • 0x1dbc220: i64 = add 0x1dbe9f0, 0x1dbc120 [ORD=13] [ID=22]
  • 0x1dbc120: i64 = Constant<20> [ORD=13] [ID=6]
  • 0x1db91c0: i64 = undef [ORD=2] [ID=3]
  • 0x1dbc620: i64 = add 0x1dbe9f0, 0x1dbc520 [ORD=17] [ID=23]
  • 0x1dbc520: i64 = Constant<4> [ORD=17] [ID=7]
  • 0x1db91c0: i64 = undef [ORD=2] [ID=3]
  • 0x1dbeaf0: i1 = or 0x1dbd640, 0x1dbe040 [ID=42]
  • 0x1dbd640: i1 = setcc 0x1dbdb40, 0x1dbdf40, 0x1db99c0 [ORD=30] [ID=38]
  • 0x1dbcc20: i64 = add 0x1dbe9f0, 0x1dbcb20 [ORD=23] [ID=24]
  • 0x1dbcb20: i64 = Constant<24> [ORD=23] [ID=8]
  • 0x1db91c0: i64 = undef [ORD=2] [ID=3]
  • 0x1dbd340: i64 = add 0x1dbe9f0, 0x1dbcf20 [ORD=27] [ID=25]
  • 0x1dbcf20: i64 = Constant<8> [ORD=27] [ID=9]
  • 0x1db91c0: i64 = undef [ORD=2] [ID=3]
  • 0x1dbe040: i1 = setcc 0x1dbedf0, 0x1dc0c20, 0x1db99c0 [ORD=40] [ID=39]
  • 0x1dbd940: i64 = add 0x1dbe9f0, 0x1dbd840 [ORD=33] [ID=26]
  • 0x1dbd840: i64 = Constant<28> [ORD=33] [ID=10]
  • 0x1db91c0: i64 = undef [ORD=2] [ID=3]
  • 0x1dbdd40: i64 = add 0x1dbe9f0, 0x1dbdc40 [ORD=37] [ID=27]
  • 0x1dbdc40: i64 = Constant<12> [ORD=37] [ID=11]
  • 0x1db91c0: i64 = undef [ORD=2] [ID=3]
  • In function: main
info 
Returncode: 1

Errors:
LLVM ERROR: Cannot select: 0x1dbe7f0: i1 = or 0x1dbe8f0, 0x1dbeaf0 [ID=43]
  0x1dbe8f0: i1 = or 0x1db9ac0, 0x1dbc920 [ID=41]
    0x1db9ac0: i1 = setcc 0x1dbc420, 0x1dbc820, 0x1db99c0 [ORD=10] [ID=36]
      0x1dbc420: i32,ch = load 0x1db8fc0, 0x1db94c0, 0x1db91c0<LD4[%1]> [ID=29]
        0x1db94c0: i64 = add 0x1dbe9f0, 0x1db93c0 [ORD=3] [ID=21]
          0x1dbe9f0: i64 = Register %vreg0 [ID=18]
          0x1db93c0: i64 = Constant<16> [ORD=3] [ID=4]
        0x1db91c0: i64 = undef [ORD=2] [ID=3]
      0x1dbc820: i32,ch = load 0x1db8fc0, 0x1dbe9f0, 0x1db91c0<LD4[%5]> [ID=28]
        0x1dbe9f0: i64 = Register %vreg0 [ID=18]
        0x1db91c0: i64 = undef [ORD=2] [ID=3]
    0x1dbc920: i1 = setcc 0x1dbce20, 0x1dbd540, 0x1db99c0 [ORD=20] [ID=37]
      0x1dbce20: i32,ch = load 0x1db8fc0, 0x1dbc220, 0x1db91c0<LD4[%11]> [ID=30]
        0x1dbc220: i64 = add 0x1dbe9f0, 0x1dbc120 [ORD=13] [ID=22]
          0x1dbe9f0: i64 = Register %vreg0 [ID=18]
          0x1dbc120: i64 = Constant<20> [ORD=13] [ID=6]
        0x1db91c0: i64 = undef [ORD=2] [ID=3]
      0x1dbd540: i32,ch = load 0x1db8fc0, 0x1dbc620, 0x1db91c0<LD4[%15]> [ID=31]
        0x1dbc620: i64 = add 0x1dbe9f0, 0x1dbc520 [ORD=17] [ID=23]
          0x1dbe9f0: i64 = Register %vreg0 [ID=18]
          0x1dbc520: i64 = Constant<4> [ORD=17] [ID=7]
        0x1db91c0: i64 = undef [ORD=2] [ID=3]
  0x1dbeaf0: i1 = or 0x1dbd640, 0x1dbe040 [ID=42]
    0x1dbd640: i1 = setcc 0x1dbdb40, 0x1dbdf40, 0x1db99c0 [ORD=30] [ID=38]
      0x1dbdb40: i32,ch = load 0x1db8fc0, 0x1dbcc20, 0x1db91c0<LD4[%21]> [ID=32]
        0x1dbcc20: i64 = add 0x1dbe9f0, 0x1dbcb20 [ORD=23] [ID=24]
          0x1dbe9f0: i64 = Register %vreg0 [ID=18]
          0x1dbcb20: i64 = Constant<24> [ORD=23] [ID=8]
        0x1db91c0: i64 = undef [ORD=2] [ID=3]
      0x1dbdf40: i32,ch = load 0x1db8fc0, 0x1dbd340, 0x1db91c0<LD4[%25]> [ID=33]
        0x1dbd340: i64 = add 0x1dbe9f0, 0x1dbcf20 [ORD=27] [ID=25]
          0x1dbe9f0: i64 = Register %vreg0 [ID=18]
          0x1dbcf20: i64 = Constant<8> [ORD=27] [ID=9]
        0x1db91c0: i64 = undef [ORD=2] [ID=3]
    0x1dbe040: i1 = setcc 0x1dbedf0, 0x1dc0c20, 0x1db99c0 [ORD=40] [ID=39]
      0x1dbedf0: i32,ch = load 0x1db8fc0, 0x1dbd940, 0x1db91c0<LD4[%31]> [ID=34]
        0x1dbd940: i64 = add 0x1dbe9f0, 0x1dbd840 [ORD=33] [ID=26]
          0x1dbe9f0: i64 = Register %vreg0 [ID=18]
          0x1dbd840: i64 = Constant<28> [ORD=33] [ID=10]
        0x1db91c0: i64 = undef [ORD=2] [ID=3]
      0x1dc0c20: i32,ch = load 0x1db8fc0, 0x1dbdd40, 0x1db91c0<LD4[%35]> [ID=35]
        0x1dbdd40: i64 = add 0x1dbe9f0, 0x1dbdc40 [ORD=37] [ID=27]
          0x1dbe9f0: i64 = Register %vreg0 [ID=18]
          0x1dbdc40: i64 = Constant<12> [ORD=37] [ID=11]
        0x1db91c0: i64 = undef [ORD=2] [ID=3]
In function: main


Output:

Back to summary