Status: fail
Result: fail
| Detail | Value |
|---|---|
| returncode | 1 |
| time | 0.0956928730011 |
| note | Returncode was 1 |
| command | /home/daenzer/src/piglit-git/piglit/framework/../bin/shader_runner tests/../generated_tests/spec/glsl-1.10/execution/built-in-functions/vs-op-div-ivec3-int.shader_test -auto |
| errors_ignored |
|
| errors |
|
| info | Returncode: 1
Errors:
LLVM ERROR: Cannot select: 0xa6ce40: i32 = truncate 0xa6ff60 [ID=99]
0xa6ff60: i64 = srl 0xa6e4a0, 0xa64530 [ID=96]
0xa6e4a0: i64 = mul 0xa6eaa0, 0xa6fe60 [ID=93]
0xa6eaa0: i64 = zero_extend 0xa70160 [ID=90]
0xa70160: i32 = select 0xa6baf0, 0xa6b1d0, 0xa6b2d0 [ID=89]
0xa6baf0: i1 = setcc 0xa70c60, 0xa5adc0, 0xa66200 [ID=81]
0xa70c60: i32 = truncate 0xa70b60 [ID=80]
0xa70b60: i64 = srl 0xa70a60, 0xa64530 [ID=79]
0xa70a60: i64 = mul 0xa70660, 0xa6b0d0 [ID=77]
0xa70660: i64 = zero_extend 0xa65230 [ID=75]
0xa6b0d0: i64 = zero_extend 0xa66000 [ID=71]
0xa64530: i64 = Constant<32> [ORD=13] [ID=10]
0xa5adc0: i32 = Constant<0> [ORD=7] [ID=6]
0xa6b1d0: i32 = add 0xa65230, 0xa70960 [ID=87]
0xa65230: i32 = URECIP 0xa66000 [ID=72]
0xa66000: i32 = xor 0xa66800, 0xa65730 [ID=67]
0xa66800: i32 = add 0xa65830, 0xa65730 [ID=61]
0xa65830: i32,ch = load 0xa5aec0:1, 0xa64c30, 0xa5a6c0<LD4[%32]> [ID=41]
0xa65730: i32 = sra 0xa65830, 0xa6add0 [ID=53]
0xa65730: i32 = sra 0xa65830, 0xa6add0 [ID=53]
0xa65830: i32,ch = load 0xa5aec0:1, 0xa64c30, 0xa5a6c0<LD4[%32]> [ID=41]
0xa6add0: i64 = Constant<31> [ID=29]
0xa70960: i32 = truncate 0xa70860 [ID=86]
0xa70860: i64 = srl 0xa70760, 0xa64530 [ID=85]
0xa70760: i64 = mul 0xa6b9f0, 0xa70660 [ID=84]
0xa6b9f0: i64 = zero_extend 0xa6b3d0 [ID=83]
0xa70660: i64 = zero_extend 0xa65230 [ID=75]
0xa64530: i64 = Constant<32> [ORD=13] [ID=10]
0xa6b2d0: i32 = sub 0xa65230, 0xa70960 [ID=88]
0xa65230: i32 = URECIP 0xa66000 [ID=72]
0xa66000: i32 = xor 0xa66800, 0xa65730 [ID=67]
0xa66800: i32 = add 0xa65830, 0xa65730 [ID=61]
0xa65830: i32,ch = load 0xa5aec0:1, 0xa64c30, 0xa5a6c0<LD4[%32]> [ID=41]
0xa65730: i32 = sra 0xa65830, 0xa6add0 [ID=53]
0xa65730: i32 = sra 0xa65830, 0xa6add0 [ID=53]
0xa65830: i32,ch = load 0xa5aec0:1, 0xa64c30, 0xa5a6c0<LD4[%32]> [ID=41]
0xa6add0: i64 = Constant<31> [ID=29]
0xa70960: i32 = truncate 0xa70860 [ID=86]
0xa70860: i64 = srl 0xa70760, 0xa64530 [ID=85]
0xa70760: i64 = mul 0xa6b9f0, 0xa70660 [ID=84]
0xa6b9f0: i64 = zero_extend 0xa6b3d0 [ID=83]
0xa70660: i64 = zero_extend 0xa65230 [ID=75]
0xa64530: i64 = Constant<32> [ORD=13] [ID=10]
0xa6fe60: i64 = zero_extend 0xa69e40 [ID=73]
0xa69e40: i32 = xor 0xa69d40, 0xa66a00 [ID=68]
0xa69d40: i32 = add 0xa65e00, 0xa66a00 [ID=63]
0xa65e00: i32,ch = load 0xa5aec0:1, 0xa65130, 0xa5a6c0<LD4[%19]> [ID=42]
0xa65130: i64 = add 0xa65430, 0xa65030 [ORD=22] [ID=33]
0xa65430: i64 = Register %vreg0 [ID=24]
0xa65030: i64 = Constant<36> [ORD=22] [ID=12]
0xa5a6c0: i64 = undef [ORD=3] [ID=4]
0xa66a00: i32 = sra 0xa65e00, 0xa6add0 [ID=55]
0xa65e00: i32,ch = load 0xa5aec0:1, 0xa65130, 0xa5a6c0<LD4[%19]> [ID=42]
0xa65130: i64 = add 0xa65430, 0xa65030 [ORD=22] [ID=33]
0xa65430: i64 = Register %vreg0 [ID=24]
0xa65030: i64 = Constant<36> [ORD=22] [ID=12]
0xa5a6c0: i64 = undef [ORD=3] [ID=4]
0xa6add0: i64 = Constant<31> [ID=29]
0xa66a00: i32 = sra 0xa65e00, 0xa6add0 [ID=55]
0xa65e00: i32,ch = load 0xa5aec0:1, 0xa65130, 0xa5a6c0<LD4[%19]> [ID=42]
0xa65130: i64 = add 0xa65430, 0xa65030 [ORD=22] [ID=33]
0xa65430: i64 = Register %vreg0 [ID=24]
0xa65030: i64 = Constant<36> [ORD=22] [ID=12]
0xa5a6c0: i64 = undef [ORD=3] [ID=4]
0xa6add0: i64 = Constant<31> [ID=29]
0xa64530: i64 = Constant<32> [ORD=13] [ID=10]
In function: main
Output:
|