Status: fail
Result: fail
Detail | Value |
---|---|
returncode | 1 |
time | 0.101274967194 |
note | Returncode was 1 |
command | /home/daenzer/src/piglit-git/piglit/framework/../bin/shader_runner tests/../generated_tests/spec/glsl-1.10/execution/built-in-functions/vs-op-div-ivec3-ivec3.shader_test -auto |
errors_ignored |
|
errors |
|
info | Returncode: 1 Errors: LLVM ERROR: Cannot select: 0x1ed34a0: i32 = truncate 0x1ed0e90 [ID=147] 0x1ed0e90: i64 = srl 0x1ed33a0, 0x1ec52a0 [ID=144] 0x1ed33a0: i64 = mul 0x1ed21e0, 0x1ed31a0 [ID=141] 0x1ed21e0: i64 = zero_extend 0x1ed32a0 [ID=138] 0x1ed32a0: i32 = select 0x1ed1be0, 0x1ed1390, 0x1ed1490 [ID=135] 0x1ed1be0: i1 = setcc 0x1ed3ba0, 0x1ebbbb0, 0x1ec7860 [ID=111] 0x1ed3ba0: i32 = truncate 0x1ed3aa0 [ID=108] 0x1ed3aa0: i64 = srl 0x1ecd450, 0x1ec52a0 [ID=105] 0x1ecd450: i64 = mul 0x1ed36a0, 0x1ed1290 [ID=101] 0x1ed36a0: i64 = zero_extend 0x1ec6640 [ID=95] 0x1ed1290: i64 = zero_extend 0x1ecbbc0 [ID=89] 0x1ec52a0: i64 = Constant<32> [ORD=13] [ID=10] 0x1ebbbb0: i32 = Constant<0> [ORD=7] [ID=6] 0x1ed1390: i32 = add 0x1ec6640, 0x1ed39a0 [ID=131] 0x1ec6640: i32 = URECIP 0x1ecbbc0 [ID=90] 0x1ecbbc0: i32 = xor 0x1ecb9c0, 0x1ecb7c0 [ID=81] 0x1ecb9c0: i32 = add 0x1ec7360, 0x1ecb7c0 [ID=75] 0x1ec7360: i32,ch = load 0x1ebbcb0:1, 0x1ec6f60, 0x1ebb4b0<LD4[%32]> [ID=49] 0x1ecb7c0: i32 = sra 0x1ec7360, 0x1ecd550 [ID=65] 0x1ecb7c0: i32 = sra 0x1ec7360, 0x1ecd550 [ID=65] 0x1ec7360: i32,ch = load 0x1ebbcb0:1, 0x1ec6f60, 0x1ebb4b0<LD4[%32]> [ID=49] 0x1ecd550: i64 = Constant<31> [ID=31] 0x1ed39a0: i32 = truncate 0x1ed37a0 [ID=126] 0x1ed37a0: i64 = srl 0x1ecf680, 0x1ec52a0 [ID=123] 0x1ecf680: i64 = mul 0x1ed1ae0, 0x1ed36a0 [ID=120] 0x1ed1ae0: i64 = zero_extend 0x1ed19e0 [ID=117] 0x1ed36a0: i64 = zero_extend 0x1ec6640 [ID=95] 0x1ec52a0: i64 = Constant<32> [ORD=13] [ID=10] 0x1ed1490: i32 = sub 0x1ec6640, 0x1ed39a0 [ID=132] 0x1ec6640: i32 = URECIP 0x1ecbbc0 [ID=90] 0x1ecbbc0: i32 = xor 0x1ecb9c0, 0x1ecb7c0 [ID=81] 0x1ecb9c0: i32 = add 0x1ec7360, 0x1ecb7c0 [ID=75] 0x1ec7360: i32,ch = load 0x1ebbcb0:1, 0x1ec6f60, 0x1ebb4b0<LD4[%32]> [ID=49] 0x1ecb7c0: i32 = sra 0x1ec7360, 0x1ecd550 [ID=65] 0x1ecb7c0: i32 = sra 0x1ec7360, 0x1ecd550 [ID=65] 0x1ec7360: i32,ch = load 0x1ebbcb0:1, 0x1ec6f60, 0x1ebb4b0<LD4[%32]> [ID=49] 0x1ecd550: i64 = Constant<31> [ID=31] 0x1ed39a0: i32 = truncate 0x1ed37a0 [ID=126] 0x1ed37a0: i64 = srl 0x1ecf680, 0x1ec52a0 [ID=123] 0x1ecf680: i64 = mul 0x1ed1ae0, 0x1ed36a0 [ID=120] 0x1ed1ae0: i64 = zero_extend 0x1ed19e0 [ID=117] 0x1ed36a0: i64 = zero_extend 0x1ec6640 [ID=95] 0x1ec52a0: i64 = Constant<32> [ORD=13] [ID=10] 0x1ed31a0: i64 = zero_extend 0x1ecbac0 [ID=88] 0x1ecbac0: i32 = xor 0x1ecb8c0, 0x1ec9ee0 [ID=80] 0x1ecb8c0: i32 = add 0x1ec7460, 0x1ec9ee0 [ID=73] 0x1ec7460: i32,ch = load 0x1ebbcb0:1, 0x1ec6840, 0x1ebb4b0<LD4[%28]> [ID=48] 0x1ec6840: i64 = add 0x1ec7260, 0x1ec6740 [ORD=31] [ID=37] 0x1ec7260: i64 = Register %vreg0 [ID=26] 0x1ec6740: i64 = Constant<40> [ORD=31] [ID=14] 0x1ebb4b0: i64 = undef [ORD=3] [ID=4] 0x1ec9ee0: i32 = sra 0x1ec7460, 0x1ecd550 [ID=63] 0x1ec7460: i32,ch = load 0x1ebbcb0:1, 0x1ec6840, 0x1ebb4b0<LD4[%28]> [ID=48] 0x1ec6840: i64 = add 0x1ec7260, 0x1ec6740 [ORD=31] [ID=37] 0x1ec7260: i64 = Register %vreg0 [ID=26] 0x1ec6740: i64 = Constant<40> [ORD=31] [ID=14] 0x1ebb4b0: i64 = undef [ORD=3] [ID=4] 0x1ecd550: i64 = Constant<31> [ID=31] 0x1ec9ee0: i32 = sra 0x1ec7460, 0x1ecd550 [ID=63] 0x1ec7460: i32,ch = load 0x1ebbcb0:1, 0x1ec6840, 0x1ebb4b0<LD4[%28]> [ID=48] 0x1ec6840: i64 = add 0x1ec7260, 0x1ec6740 [ORD=31] [ID=37] 0x1ec7260: i64 = Register %vreg0 [ID=26] 0x1ec6740: i64 = Constant<40> [ORD=31] [ID=14] 0x1ebb4b0: i64 = undef [ORD=3] [ID=4] 0x1ecd550: i64 = Constant<31> [ID=31] 0x1ec52a0: i64 = Constant<32> [ORD=13] [ID=10] In function: main Output: |