Results for spec/glsl-1.10/execution/built-in-functions/vs-op-eq-bvec2-bvec2

Overview

Status: fail
Result: fail

Back to summary

Details

Detail Value
returncode 1
time 0.105855941772
note 
Returncode was 1
command 
/home/daenzer/src/piglit-git/piglit/framework/../bin/shader_runner tests/../generated_tests/spec/glsl-1.10/execution/built-in-functions/vs-op-eq-bvec2-bvec2.shader_test -auto
errors_ignored 
  • 0x16cea10: i32,ch = load 0x16cabd0:1, 0x16cdd10, 0x16ca3d0<LD4[%10]> [ID=30]
  • 0x16cf660: i64 = Register %vreg0 [ID=20]
  • 0x16cee10: i32,ch = load 0x16cabd0:1, 0x16cf660, 0x16ca3d0<LD4[%14]> [ID=31]
  • 0x16cf660: i64 = Register %vreg0 [ID=20]
  • 0x16d1990: i32,ch = load 0x16cabd0:1, 0x16ce810, 0x16ca3d0<LD4[%20]> [ID=32]
  • 0x16cf660: i64 = Register %vreg0 [ID=20]
  • 0x16cf560: i32,ch = load 0x16cabd0:1, 0x16cec10, 0x16ca3d0<LD4[%24]> [ID=33]
  • 0x16cf660: i64 = Register %vreg0 [ID=20]
errors 
  • LLVM ERROR: Cannot select: 0x16cfa60: i32 = sign_extend 0x16ce310 [ID=45]
  • 0x16ce310: i1 = VCC_BITCAST 0x16cd810 [ID=44]
  • 0x16cd810: i64 = and 0x16cd510, 0x16ca0d0 [ID=43]
  • 0x16cd510: i64 = VCC_BITCAST 0x16ce510 [ID=41]
  • 0x16ce510: i1 = setcc 0x16cea10, 0x16cee10, 0x16ce410 [ORD=20] [ID=38]
  • 0x16cdd10: i64 = add 0x16cf660, 0x16cdc10 [ORD=13] [ID=24]
  • 0x16cdc10: i64 = Constant<16> [ORD=13] [ID=10]
  • 0x16ca3d0: i64 = undef [ORD=3] [ID=4]
  • 0x16ca3d0: i64 = undef [ORD=3] [ID=4]
  • 0x16ca0d0: i64 = VCC_BITCAST 0x16cef10 [ID=42]
  • 0x16cef10: i1 = setcc 0x16d1990, 0x16cf560, 0x16ce410 [ORD=30] [ID=39]
  • 0x16ce810: i64 = add 0x16cf660, 0x16ce710 [ORD=23] [ID=25]
  • 0x16ce710: i64 = Constant<20> [ORD=23] [ID=12]
  • 0x16ca3d0: i64 = undef [ORD=3] [ID=4]
  • 0x16cec10: i64 = add 0x16cf660, 0x16ceb10 [ORD=27] [ID=26]
  • 0x16ceb10: i64 = Constant<4> [ORD=27] [ID=13]
  • 0x16ca3d0: i64 = undef [ORD=3] [ID=4]
  • In function: main
info 
Returncode: 1

Errors:
LLVM ERROR: Cannot select: 0x16cfa60: i32 = sign_extend 0x16ce310 [ID=45]
  0x16ce310: i1 = VCC_BITCAST 0x16cd810 [ID=44]
    0x16cd810: i64 = and 0x16cd510, 0x16ca0d0 [ID=43]
      0x16cd510: i64 = VCC_BITCAST 0x16ce510 [ID=41]
        0x16ce510: i1 = setcc 0x16cea10, 0x16cee10, 0x16ce410 [ORD=20] [ID=38]
          0x16cea10: i32,ch = load 0x16cabd0:1, 0x16cdd10, 0x16ca3d0<LD4[%10]> [ID=30]
            0x16cdd10: i64 = add 0x16cf660, 0x16cdc10 [ORD=13] [ID=24]
              0x16cf660: i64 = Register %vreg0 [ID=20]
              0x16cdc10: i64 = Constant<16> [ORD=13] [ID=10]
            0x16ca3d0: i64 = undef [ORD=3] [ID=4]
          0x16cee10: i32,ch = load 0x16cabd0:1, 0x16cf660, 0x16ca3d0<LD4[%14]> [ID=31]
            0x16cf660: i64 = Register %vreg0 [ID=20]
            0x16ca3d0: i64 = undef [ORD=3] [ID=4]
      0x16ca0d0: i64 = VCC_BITCAST 0x16cef10 [ID=42]
        0x16cef10: i1 = setcc 0x16d1990, 0x16cf560, 0x16ce410 [ORD=30] [ID=39]
          0x16d1990: i32,ch = load 0x16cabd0:1, 0x16ce810, 0x16ca3d0<LD4[%20]> [ID=32]
            0x16ce810: i64 = add 0x16cf660, 0x16ce710 [ORD=23] [ID=25]
              0x16cf660: i64 = Register %vreg0 [ID=20]
              0x16ce710: i64 = Constant<20> [ORD=23] [ID=12]
            0x16ca3d0: i64 = undef [ORD=3] [ID=4]
          0x16cf560: i32,ch = load 0x16cabd0:1, 0x16cec10, 0x16ca3d0<LD4[%24]> [ID=33]
            0x16cec10: i64 = add 0x16cf660, 0x16ceb10 [ORD=27] [ID=26]
              0x16cf660: i64 = Register %vreg0 [ID=20]
              0x16ceb10: i64 = Constant<4> [ORD=27] [ID=13]
            0x16ca3d0: i64 = undef [ORD=3] [ID=4]
In function: main


Output:

Back to summary