Results for spec/glsl-1.10/execution/built-in-functions/vs-op-ne-bvec4-bvec4

Overview

Status: fail
Result: fail

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Details

Detail Value
returncode 1
time 0.10010099411
note 
Returncode was 1
command 
/home/daenzer/src/piglit-git/piglit/framework/../bin/shader_runner tests/../generated_tests/spec/glsl-1.10/execution/built-in-functions/vs-op-ne-bvec4-bvec4.shader_test -auto
errors_ignored 
  • 0x1f2dfb0: i32,ch = load 0x1f08e10:1, 0x1f2d300, 0x1f08610<LD4[%10]> [ID=38]
  • 0x1f08310: i64 = Register %vreg0 [ID=24]
  • 0x1f2e3b0: i32,ch = load 0x1f08e10:1, 0x1f08310, 0x1f08610<LD4[%14]> [ID=39]
  • 0x1f08310: i64 = Register %vreg0 [ID=24]
  • 0x1f2ed90: i32,ch = load 0x1f08e10:1, 0x1f2ddb0, 0x1f08610<LD4[%20]> [ID=40]
  • 0x1f08310: i64 = Register %vreg0 [ID=24]
  • 0x1f2f190: i32,ch = load 0x1f08e10:1, 0x1f2e1b0, 0x1f08610<LD4[%24]> [ID=41]
  • 0x1f08310: i64 = Register %vreg0 [ID=24]
  • 0x1f2f790: i32,ch = load 0x1f08e10:1, 0x1f2eb90, 0x1f08610<LD4[%30]> [ID=42]
  • 0x1f08310: i64 = Register %vreg0 [ID=24]
  • 0x1f31110: i32,ch = load 0x1f08e10:1, 0x1f2ef90, 0x1f08610<LD4[%34]> [ID=43]
  • 0x1f08310: i64 = Register %vreg0 [ID=24]
  • 0x1f31d10: i32,ch = load 0x1f08e10:1, 0x1f2f590, 0x1f08610<LD4[%40]> [ID=44]
  • 0x1f08310: i64 = Register %vreg0 [ID=24]
  • 0x1f31a10: i32,ch = load 0x1f08e10:1, 0x1f2f990, 0x1f08610<LD4[%44]> [ID=45]
  • 0x1f08310: i64 = Register %vreg0 [ID=24]
errors 
  • LLVM ERROR: Cannot select: 0x1f32220: i32 = sign_extend 0x1f31810 [ID=58]
  • 0x1f31810: i1 = or 0x1f31910, 0x1f31b10 [ID=57]
  • 0x1f31910: i1 = or 0x1f2dab0, 0x1f2e4b0 [ID=55]
  • 0x1f2dab0: i1 = setcc 0x1f2dfb0, 0x1f2e3b0, 0x1f2d9b0 [ORD=20] [ID=50]
  • 0x1f2d300: i64 = add 0x1f08310, 0x1f2d200 [ORD=13] [ID=28]
  • 0x1f2d200: i64 = Constant<16> [ORD=13] [ID=10]
  • 0x1f08610: i64 = undef [ORD=3] [ID=4]
  • 0x1f08610: i64 = undef [ORD=3] [ID=4]
  • 0x1f2e4b0: i1 = setcc 0x1f2ed90, 0x1f2f190, 0x1f2d9b0 [ORD=30] [ID=51]
  • 0x1f2ddb0: i64 = add 0x1f08310, 0x1f2dcb0 [ORD=23] [ID=29]
  • 0x1f2dcb0: i64 = Constant<20> [ORD=23] [ID=12]
  • 0x1f08610: i64 = undef [ORD=3] [ID=4]
  • 0x1f2e1b0: i64 = add 0x1f08310, 0x1f2e0b0 [ORD=27] [ID=30]
  • 0x1f2e0b0: i64 = Constant<4> [ORD=27] [ID=13]
  • 0x1f08610: i64 = undef [ORD=3] [ID=4]
  • 0x1f31b10: i1 = or 0x1f2f290, 0x1f31210 [ID=56]
  • 0x1f2f290: i1 = setcc 0x1f2f790, 0x1f31110, 0x1f2d9b0 [ORD=40] [ID=52]
  • 0x1f2eb90: i64 = add 0x1f08310, 0x1f2e6b0 [ORD=33] [ID=31]
  • 0x1f2e6b0: i64 = Constant<24> [ORD=33] [ID=14]
  • 0x1f08610: i64 = undef [ORD=3] [ID=4]
  • 0x1f2ef90: i64 = add 0x1f08310, 0x1f2ee90 [ORD=37] [ID=32]
  • 0x1f2ee90: i64 = Constant<8> [ORD=37] [ID=15]
  • 0x1f08610: i64 = undef [ORD=3] [ID=4]
  • 0x1f31210: i1 = setcc 0x1f31d10, 0x1f31a10, 0x1f2d9b0 [ORD=50] [ID=53]
  • 0x1f2f590: i64 = add 0x1f08310, 0x1f2f490 [ORD=43] [ID=33]
  • 0x1f2f490: i64 = Constant<28> [ORD=43] [ID=16]
  • 0x1f08610: i64 = undef [ORD=3] [ID=4]
  • 0x1f2f990: i64 = add 0x1f08310, 0x1f2f890 [ORD=47] [ID=34]
  • 0x1f2f890: i64 = Constant<12> [ORD=47] [ID=17]
  • 0x1f08610: i64 = undef [ORD=3] [ID=4]
  • In function: main
info 
Returncode: 1

Errors:
LLVM ERROR: Cannot select: 0x1f32220: i32 = sign_extend 0x1f31810 [ID=58]
  0x1f31810: i1 = or 0x1f31910, 0x1f31b10 [ID=57]
    0x1f31910: i1 = or 0x1f2dab0, 0x1f2e4b0 [ID=55]
      0x1f2dab0: i1 = setcc 0x1f2dfb0, 0x1f2e3b0, 0x1f2d9b0 [ORD=20] [ID=50]
        0x1f2dfb0: i32,ch = load 0x1f08e10:1, 0x1f2d300, 0x1f08610<LD4[%10]> [ID=38]
          0x1f2d300: i64 = add 0x1f08310, 0x1f2d200 [ORD=13] [ID=28]
            0x1f08310: i64 = Register %vreg0 [ID=24]
            0x1f2d200: i64 = Constant<16> [ORD=13] [ID=10]
          0x1f08610: i64 = undef [ORD=3] [ID=4]
        0x1f2e3b0: i32,ch = load 0x1f08e10:1, 0x1f08310, 0x1f08610<LD4[%14]> [ID=39]
          0x1f08310: i64 = Register %vreg0 [ID=24]
          0x1f08610: i64 = undef [ORD=3] [ID=4]
      0x1f2e4b0: i1 = setcc 0x1f2ed90, 0x1f2f190, 0x1f2d9b0 [ORD=30] [ID=51]
        0x1f2ed90: i32,ch = load 0x1f08e10:1, 0x1f2ddb0, 0x1f08610<LD4[%20]> [ID=40]
          0x1f2ddb0: i64 = add 0x1f08310, 0x1f2dcb0 [ORD=23] [ID=29]
            0x1f08310: i64 = Register %vreg0 [ID=24]
            0x1f2dcb0: i64 = Constant<20> [ORD=23] [ID=12]
          0x1f08610: i64 = undef [ORD=3] [ID=4]
        0x1f2f190: i32,ch = load 0x1f08e10:1, 0x1f2e1b0, 0x1f08610<LD4[%24]> [ID=41]
          0x1f2e1b0: i64 = add 0x1f08310, 0x1f2e0b0 [ORD=27] [ID=30]
            0x1f08310: i64 = Register %vreg0 [ID=24]
            0x1f2e0b0: i64 = Constant<4> [ORD=27] [ID=13]
          0x1f08610: i64 = undef [ORD=3] [ID=4]
    0x1f31b10: i1 = or 0x1f2f290, 0x1f31210 [ID=56]
      0x1f2f290: i1 = setcc 0x1f2f790, 0x1f31110, 0x1f2d9b0 [ORD=40] [ID=52]
        0x1f2f790: i32,ch = load 0x1f08e10:1, 0x1f2eb90, 0x1f08610<LD4[%30]> [ID=42]
          0x1f2eb90: i64 = add 0x1f08310, 0x1f2e6b0 [ORD=33] [ID=31]
            0x1f08310: i64 = Register %vreg0 [ID=24]
            0x1f2e6b0: i64 = Constant<24> [ORD=33] [ID=14]
          0x1f08610: i64 = undef [ORD=3] [ID=4]
        0x1f31110: i32,ch = load 0x1f08e10:1, 0x1f2ef90, 0x1f08610<LD4[%34]> [ID=43]
          0x1f2ef90: i64 = add 0x1f08310, 0x1f2ee90 [ORD=37] [ID=32]
            0x1f08310: i64 = Register %vreg0 [ID=24]
            0x1f2ee90: i64 = Constant<8> [ORD=37] [ID=15]
          0x1f08610: i64 = undef [ORD=3] [ID=4]
      0x1f31210: i1 = setcc 0x1f31d10, 0x1f31a10, 0x1f2d9b0 [ORD=50] [ID=53]
        0x1f31d10: i32,ch = load 0x1f08e10:1, 0x1f2f590, 0x1f08610<LD4[%40]> [ID=44]
          0x1f2f590: i64 = add 0x1f08310, 0x1f2f490 [ORD=43] [ID=33]
            0x1f08310: i64 = Register %vreg0 [ID=24]
            0x1f2f490: i64 = Constant<28> [ORD=43] [ID=16]
          0x1f08610: i64 = undef [ORD=3] [ID=4]
        0x1f31a10: i32,ch = load 0x1f08e10:1, 0x1f2f990, 0x1f08610<LD4[%44]> [ID=45]
          0x1f2f990: i64 = add 0x1f08310, 0x1f2f890 [ORD=47] [ID=34]
            0x1f08310: i64 = Register %vreg0 [ID=24]
            0x1f2f890: i64 = Constant<12> [ORD=47] [ID=17]
          0x1f08610: i64 = undef [ORD=3] [ID=4]
In function: main


Output:

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