Results for spec/glsl-1.10/execution/built-in-functions/vs-op-ne-bvec4-bvec4-using-if

Overview

Status: fail
Result: fail

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Details

Detail Value
returncode 1
time 0.100770950317
note 
Returncode was 1
command 
/home/daenzer/src/piglit-git/piglit/framework/../bin/shader_runner tests/../generated_tests/spec/glsl-1.10/execution/built-in-functions/vs-op-ne-bvec4-bvec4-using-if.shader_test -auto
errors_ignored 
  • 0x1acf780: i32,ch = load 0x1aa87e0:1, 0x1aceb70, 0x1aa7fe0<LD4[%10]> [ID=38]
  • 0x1ad2ec0: i64 = Register %vreg0 [ID=24]
  • 0x1acfb80: i32,ch = load 0x1aa87e0:1, 0x1ad2ec0, 0x1aa7fe0<LD4[%14]> [ID=39]
  • 0x1ad2ec0: i64 = Register %vreg0 [ID=24]
  • 0x1ad0290: i32,ch = load 0x1aa87e0:1, 0x1acf580, 0x1aa7fe0<LD4[%20]> [ID=40]
  • 0x1ad2ec0: i64 = Register %vreg0 [ID=24]
  • 0x1ad0690: i32,ch = load 0x1aa87e0:1, 0x1acf980, 0x1aa7fe0<LD4[%24]> [ID=41]
  • 0x1ad2ec0: i64 = Register %vreg0 [ID=24]
  • 0x1ad0c90: i32,ch = load 0x1aa87e0:1, 0x1ad0090, 0x1aa7fe0<LD4[%30]> [ID=42]
  • 0x1ad2ec0: i64 = Register %vreg0 [ID=24]
  • 0x1ad25c0: i32,ch = load 0x1aa87e0:1, 0x1ad0490, 0x1aa7fe0<LD4[%34]> [ID=43]
  • 0x1ad2ec0: i64 = Register %vreg0 [ID=24]
  • 0x1ad32c0: i32,ch = load 0x1aa87e0:1, 0x1ad0a90, 0x1aa7fe0<LD4[%40]> [ID=44]
  • 0x1ad2ec0: i64 = Register %vreg0 [ID=24]
  • 0x1ad38d0: i32,ch = load 0x1aa87e0:1, 0x1ad0e90, 0x1aa7fe0<LD4[%44]> [ID=45]
  • 0x1ad2ec0: i64 = Register %vreg0 [ID=24]
errors 
  • LLVM ERROR: Cannot select: 0x1ad2cc0: i1 = or 0x1ad2dc0, 0x1ad2fc0 [ID=57]
  • 0x1ad2dc0: i1 = or 0x1acf280, 0x1acfc80 [ID=55]
  • 0x1acf280: i1 = setcc 0x1acf780, 0x1acfb80, 0x1acf180 [ORD=20] [ID=50]
  • 0x1aceb70: i64 = add 0x1ad2ec0, 0x1acea70 [ORD=13] [ID=28]
  • 0x1acea70: i64 = Constant<16> [ORD=13] [ID=10]
  • 0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
  • 0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
  • 0x1acfc80: i1 = setcc 0x1ad0290, 0x1ad0690, 0x1acf180 [ORD=30] [ID=51]
  • 0x1acf580: i64 = add 0x1ad2ec0, 0x1acf480 [ORD=23] [ID=29]
  • 0x1acf480: i64 = Constant<20> [ORD=23] [ID=12]
  • 0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
  • 0x1acf980: i64 = add 0x1ad2ec0, 0x1acf880 [ORD=27] [ID=30]
  • 0x1acf880: i64 = Constant<4> [ORD=27] [ID=13]
  • 0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
  • 0x1ad2fc0: i1 = or 0x1ad0790, 0x1ad26c0 [ID=56]
  • 0x1ad0790: i1 = setcc 0x1ad0c90, 0x1ad25c0, 0x1acf180 [ORD=40] [ID=52]
  • 0x1ad0090: i64 = add 0x1ad2ec0, 0x1acfe80 [ORD=33] [ID=31]
  • 0x1acfe80: i64 = Constant<24> [ORD=33] [ID=14]
  • 0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
  • 0x1ad0490: i64 = add 0x1ad2ec0, 0x1ad0390 [ORD=37] [ID=32]
  • 0x1ad0390: i64 = Constant<8> [ORD=37] [ID=15]
  • 0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
  • 0x1ad26c0: i1 = setcc 0x1ad32c0, 0x1ad38d0, 0x1acf180 [ORD=50] [ID=53]
  • 0x1ad0a90: i64 = add 0x1ad2ec0, 0x1ad0990 [ORD=43] [ID=33]
  • 0x1ad0990: i64 = Constant<28> [ORD=43] [ID=16]
  • 0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
  • 0x1ad0e90: i64 = add 0x1ad2ec0, 0x1ad0d90 [ORD=47] [ID=34]
  • 0x1ad0d90: i64 = Constant<12> [ORD=47] [ID=17]
  • 0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
  • In function: main
info 
Returncode: 1

Errors:
LLVM ERROR: Cannot select: 0x1ad2cc0: i1 = or 0x1ad2dc0, 0x1ad2fc0 [ID=57]
  0x1ad2dc0: i1 = or 0x1acf280, 0x1acfc80 [ID=55]
    0x1acf280: i1 = setcc 0x1acf780, 0x1acfb80, 0x1acf180 [ORD=20] [ID=50]
      0x1acf780: i32,ch = load 0x1aa87e0:1, 0x1aceb70, 0x1aa7fe0<LD4[%10]> [ID=38]
        0x1aceb70: i64 = add 0x1ad2ec0, 0x1acea70 [ORD=13] [ID=28]
          0x1ad2ec0: i64 = Register %vreg0 [ID=24]
          0x1acea70: i64 = Constant<16> [ORD=13] [ID=10]
        0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
      0x1acfb80: i32,ch = load 0x1aa87e0:1, 0x1ad2ec0, 0x1aa7fe0<LD4[%14]> [ID=39]
        0x1ad2ec0: i64 = Register %vreg0 [ID=24]
        0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
    0x1acfc80: i1 = setcc 0x1ad0290, 0x1ad0690, 0x1acf180 [ORD=30] [ID=51]
      0x1ad0290: i32,ch = load 0x1aa87e0:1, 0x1acf580, 0x1aa7fe0<LD4[%20]> [ID=40]
        0x1acf580: i64 = add 0x1ad2ec0, 0x1acf480 [ORD=23] [ID=29]
          0x1ad2ec0: i64 = Register %vreg0 [ID=24]
          0x1acf480: i64 = Constant<20> [ORD=23] [ID=12]
        0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
      0x1ad0690: i32,ch = load 0x1aa87e0:1, 0x1acf980, 0x1aa7fe0<LD4[%24]> [ID=41]
        0x1acf980: i64 = add 0x1ad2ec0, 0x1acf880 [ORD=27] [ID=30]
          0x1ad2ec0: i64 = Register %vreg0 [ID=24]
          0x1acf880: i64 = Constant<4> [ORD=27] [ID=13]
        0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
  0x1ad2fc0: i1 = or 0x1ad0790, 0x1ad26c0 [ID=56]
    0x1ad0790: i1 = setcc 0x1ad0c90, 0x1ad25c0, 0x1acf180 [ORD=40] [ID=52]
      0x1ad0c90: i32,ch = load 0x1aa87e0:1, 0x1ad0090, 0x1aa7fe0<LD4[%30]> [ID=42]
        0x1ad0090: i64 = add 0x1ad2ec0, 0x1acfe80 [ORD=33] [ID=31]
          0x1ad2ec0: i64 = Register %vreg0 [ID=24]
          0x1acfe80: i64 = Constant<24> [ORD=33] [ID=14]
        0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
      0x1ad25c0: i32,ch = load 0x1aa87e0:1, 0x1ad0490, 0x1aa7fe0<LD4[%34]> [ID=43]
        0x1ad0490: i64 = add 0x1ad2ec0, 0x1ad0390 [ORD=37] [ID=32]
          0x1ad2ec0: i64 = Register %vreg0 [ID=24]
          0x1ad0390: i64 = Constant<8> [ORD=37] [ID=15]
        0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
    0x1ad26c0: i1 = setcc 0x1ad32c0, 0x1ad38d0, 0x1acf180 [ORD=50] [ID=53]
      0x1ad32c0: i32,ch = load 0x1aa87e0:1, 0x1ad0a90, 0x1aa7fe0<LD4[%40]> [ID=44]
        0x1ad0a90: i64 = add 0x1ad2ec0, 0x1ad0990 [ORD=43] [ID=33]
          0x1ad2ec0: i64 = Register %vreg0 [ID=24]
          0x1ad0990: i64 = Constant<28> [ORD=43] [ID=16]
        0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
      0x1ad38d0: i32,ch = load 0x1aa87e0:1, 0x1ad0e90, 0x1aa7fe0<LD4[%44]> [ID=45]
        0x1ad0e90: i64 = add 0x1ad2ec0, 0x1ad0d90 [ORD=47] [ID=34]
          0x1ad2ec0: i64 = Register %vreg0 [ID=24]
          0x1ad0d90: i64 = Constant<12> [ORD=47] [ID=17]
        0x1aa7fe0: i64 = undef [ORD=3] [ID=4]
In function: main


Output:

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