Results for spec/glsl-1.10/execution/built-in-functions/vs-op-ne-ivec2-ivec2-using-if

Overview

Status: fail
Result: fail

Back to summary

Details

Detail Value
returncode 1
time 0.0666778087616
note 
Returncode was 1
command 
/home/daenzer/src/piglit-git/piglit/framework/../bin/shader_runner tests/../generated_tests/spec/glsl-1.10/execution/built-in-functions/vs-op-ne-ivec2-ivec2-using-if.shader_test -auto
errors_ignored 
  • 0x12be7c0: i32,ch = load 0x12ba980:1, 0x12bdac0, 0x12ba180<LD4[%10]> [ID=30]
  • 0x12bf330: i64 = Register %vreg0 [ID=20]
  • 0x12bebc0: i32,ch = load 0x12ba980:1, 0x12bf330, 0x12ba180<LD4[%14]> [ID=31]
  • 0x12bf330: i64 = Register %vreg0 [ID=20]
  • 0x12bf530: i32,ch = load 0x12ba980:1, 0x12be5c0, 0x12ba180<LD4[%20]> [ID=32]
  • 0x12bf330: i64 = Register %vreg0 [ID=20]
  • 0x12bfa30: i32,ch = load 0x12ba980:1, 0x12be9c0, 0x12ba180<LD4[%24]> [ID=33]
  • 0x12bf330: i64 = Register %vreg0 [ID=20]
errors 
  • LLVM ERROR: Cannot select: 0x12bf430: i1 = or 0x12be2c0, 0x12becc0 [ID=41]
  • 0x12be2c0: i1 = setcc 0x12be7c0, 0x12bebc0, 0x12be1c0 [ORD=20] [ID=38]
  • 0x12bdac0: i64 = add 0x12bf330, 0x12bd9c0 [ORD=13] [ID=24]
  • 0x12bd9c0: i64 = Constant<16> [ORD=13] [ID=10]
  • 0x12ba180: i64 = undef [ORD=3] [ID=4]
  • 0x12ba180: i64 = undef [ORD=3] [ID=4]
  • 0x12becc0: i1 = setcc 0x12bf530, 0x12bfa30, 0x12be1c0 [ORD=30] [ID=39]
  • 0x12be5c0: i64 = add 0x12bf330, 0x12be4c0 [ORD=23] [ID=25]
  • 0x12be4c0: i64 = Constant<20> [ORD=23] [ID=12]
  • 0x12ba180: i64 = undef [ORD=3] [ID=4]
  • 0x12be9c0: i64 = add 0x12bf330, 0x12be8c0 [ORD=27] [ID=26]
  • 0x12be8c0: i64 = Constant<4> [ORD=27] [ID=13]
  • 0x12ba180: i64 = undef [ORD=3] [ID=4]
  • In function: main
info 
Returncode: 1

Errors:
LLVM ERROR: Cannot select: 0x12bf430: i1 = or 0x12be2c0, 0x12becc0 [ID=41]
  0x12be2c0: i1 = setcc 0x12be7c0, 0x12bebc0, 0x12be1c0 [ORD=20] [ID=38]
    0x12be7c0: i32,ch = load 0x12ba980:1, 0x12bdac0, 0x12ba180<LD4[%10]> [ID=30]
      0x12bdac0: i64 = add 0x12bf330, 0x12bd9c0 [ORD=13] [ID=24]
        0x12bf330: i64 = Register %vreg0 [ID=20]
        0x12bd9c0: i64 = Constant<16> [ORD=13] [ID=10]
      0x12ba180: i64 = undef [ORD=3] [ID=4]
    0x12bebc0: i32,ch = load 0x12ba980:1, 0x12bf330, 0x12ba180<LD4[%14]> [ID=31]
      0x12bf330: i64 = Register %vreg0 [ID=20]
      0x12ba180: i64 = undef [ORD=3] [ID=4]
  0x12becc0: i1 = setcc 0x12bf530, 0x12bfa30, 0x12be1c0 [ORD=30] [ID=39]
    0x12bf530: i32,ch = load 0x12ba980:1, 0x12be5c0, 0x12ba180<LD4[%20]> [ID=32]
      0x12be5c0: i64 = add 0x12bf330, 0x12be4c0 [ORD=23] [ID=25]
        0x12bf330: i64 = Register %vreg0 [ID=20]
        0x12be4c0: i64 = Constant<20> [ORD=23] [ID=12]
      0x12ba180: i64 = undef [ORD=3] [ID=4]
    0x12bfa30: i32,ch = load 0x12ba980:1, 0x12be9c0, 0x12ba180<LD4[%24]> [ID=33]
      0x12be9c0: i64 = add 0x12bf330, 0x12be8c0 [ORD=27] [ID=26]
        0x12bf330: i64 = Register %vreg0 [ID=20]
        0x12be8c0: i64 = Constant<4> [ORD=27] [ID=13]
      0x12ba180: i64 = undef [ORD=3] [ID=4]
In function: main


Output:

Back to summary