Results for spec/glsl-1.10/execution/built-in-functions/vs-op-ne-ivec4-ivec4

Overview

Status: fail
Result: fail

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Details

Detail Value
returncode 1
time 0.0903739929199
note 
Returncode was 1
command 
/home/daenzer/src/piglit-git/piglit/framework/../bin/shader_runner tests/../generated_tests/spec/glsl-1.10/execution/built-in-functions/vs-op-ne-ivec4-ivec4.shader_test -auto
errors_ignored 
  • 0x195cd80: i32,ch = load 0x1958f40:1, 0x195c080, 0x1958740<LD4[%10]> [ID=38]
  • 0x1958440: i64 = Register %vreg0 [ID=24]
  • 0x195d180: i32,ch = load 0x1958f40:1, 0x1958440, 0x1958740<LD4[%14]> [ID=39]
  • 0x1958440: i64 = Register %vreg0 [ID=24]
  • 0x195db60: i32,ch = load 0x1958f40:1, 0x195cb80, 0x1958740<LD4[%20]> [ID=40]
  • 0x1958440: i64 = Register %vreg0 [ID=24]
  • 0x195df60: i32,ch = load 0x1958f40:1, 0x195cf80, 0x1958740<LD4[%24]> [ID=41]
  • 0x1958440: i64 = Register %vreg0 [ID=24]
  • 0x195e560: i32,ch = load 0x1958f40:1, 0x195d960, 0x1958740<LD4[%30]> [ID=42]
  • 0x1958440: i64 = Register %vreg0 [ID=24]
  • 0x195fee0: i32,ch = load 0x1958f40:1, 0x195dd60, 0x1958740<LD4[%34]> [ID=43]
  • 0x1958440: i64 = Register %vreg0 [ID=24]
  • 0x1960ae0: i32,ch = load 0x1958f40:1, 0x195e360, 0x1958740<LD4[%40]> [ID=44]
  • 0x1958440: i64 = Register %vreg0 [ID=24]
  • 0x19607e0: i32,ch = load 0x1958f40:1, 0x195e760, 0x1958740<LD4[%44]> [ID=45]
  • 0x1958440: i64 = Register %vreg0 [ID=24]
errors 
  • LLVM ERROR: Cannot select: 0x1960ff0: i32 = sign_extend 0x19605e0 [ID=58]
  • 0x19605e0: i1 = or 0x19606e0, 0x19608e0 [ID=57]
  • 0x19606e0: i1 = or 0x195c880, 0x195d280 [ID=55]
  • 0x195c880: i1 = setcc 0x195cd80, 0x195d180, 0x195c780 [ORD=20] [ID=50]
  • 0x195c080: i64 = add 0x1958440, 0x195bf80 [ORD=13] [ID=28]
  • 0x195bf80: i64 = Constant<16> [ORD=13] [ID=10]
  • 0x1958740: i64 = undef [ORD=3] [ID=4]
  • 0x1958740: i64 = undef [ORD=3] [ID=4]
  • 0x195d280: i1 = setcc 0x195db60, 0x195df60, 0x195c780 [ORD=30] [ID=51]
  • 0x195cb80: i64 = add 0x1958440, 0x195ca80 [ORD=23] [ID=29]
  • 0x195ca80: i64 = Constant<20> [ORD=23] [ID=12]
  • 0x1958740: i64 = undef [ORD=3] [ID=4]
  • 0x195cf80: i64 = add 0x1958440, 0x195ce80 [ORD=27] [ID=30]
  • 0x195ce80: i64 = Constant<4> [ORD=27] [ID=13]
  • 0x1958740: i64 = undef [ORD=3] [ID=4]
  • 0x19608e0: i1 = or 0x195e060, 0x195ffe0 [ID=56]
  • 0x195e060: i1 = setcc 0x195e560, 0x195fee0, 0x195c780 [ORD=40] [ID=52]
  • 0x195d960: i64 = add 0x1958440, 0x195d480 [ORD=33] [ID=31]
  • 0x195d480: i64 = Constant<24> [ORD=33] [ID=14]
  • 0x1958740: i64 = undef [ORD=3] [ID=4]
  • 0x195dd60: i64 = add 0x1958440, 0x195dc60 [ORD=37] [ID=32]
  • 0x195dc60: i64 = Constant<8> [ORD=37] [ID=15]
  • 0x1958740: i64 = undef [ORD=3] [ID=4]
  • 0x195ffe0: i1 = setcc 0x1960ae0, 0x19607e0, 0x195c780 [ORD=50] [ID=53]
  • 0x195e360: i64 = add 0x1958440, 0x195e260 [ORD=43] [ID=33]
  • 0x195e260: i64 = Constant<28> [ORD=43] [ID=16]
  • 0x1958740: i64 = undef [ORD=3] [ID=4]
  • 0x195e760: i64 = add 0x1958440, 0x195e660 [ORD=47] [ID=34]
  • 0x195e660: i64 = Constant<12> [ORD=47] [ID=17]
  • 0x1958740: i64 = undef [ORD=3] [ID=4]
  • In function: main
info 
Returncode: 1

Errors:
LLVM ERROR: Cannot select: 0x1960ff0: i32 = sign_extend 0x19605e0 [ID=58]
  0x19605e0: i1 = or 0x19606e0, 0x19608e0 [ID=57]
    0x19606e0: i1 = or 0x195c880, 0x195d280 [ID=55]
      0x195c880: i1 = setcc 0x195cd80, 0x195d180, 0x195c780 [ORD=20] [ID=50]
        0x195cd80: i32,ch = load 0x1958f40:1, 0x195c080, 0x1958740<LD4[%10]> [ID=38]
          0x195c080: i64 = add 0x1958440, 0x195bf80 [ORD=13] [ID=28]
            0x1958440: i64 = Register %vreg0 [ID=24]
            0x195bf80: i64 = Constant<16> [ORD=13] [ID=10]
          0x1958740: i64 = undef [ORD=3] [ID=4]
        0x195d180: i32,ch = load 0x1958f40:1, 0x1958440, 0x1958740<LD4[%14]> [ID=39]
          0x1958440: i64 = Register %vreg0 [ID=24]
          0x1958740: i64 = undef [ORD=3] [ID=4]
      0x195d280: i1 = setcc 0x195db60, 0x195df60, 0x195c780 [ORD=30] [ID=51]
        0x195db60: i32,ch = load 0x1958f40:1, 0x195cb80, 0x1958740<LD4[%20]> [ID=40]
          0x195cb80: i64 = add 0x1958440, 0x195ca80 [ORD=23] [ID=29]
            0x1958440: i64 = Register %vreg0 [ID=24]
            0x195ca80: i64 = Constant<20> [ORD=23] [ID=12]
          0x1958740: i64 = undef [ORD=3] [ID=4]
        0x195df60: i32,ch = load 0x1958f40:1, 0x195cf80, 0x1958740<LD4[%24]> [ID=41]
          0x195cf80: i64 = add 0x1958440, 0x195ce80 [ORD=27] [ID=30]
            0x1958440: i64 = Register %vreg0 [ID=24]
            0x195ce80: i64 = Constant<4> [ORD=27] [ID=13]
          0x1958740: i64 = undef [ORD=3] [ID=4]
    0x19608e0: i1 = or 0x195e060, 0x195ffe0 [ID=56]
      0x195e060: i1 = setcc 0x195e560, 0x195fee0, 0x195c780 [ORD=40] [ID=52]
        0x195e560: i32,ch = load 0x1958f40:1, 0x195d960, 0x1958740<LD4[%30]> [ID=42]
          0x195d960: i64 = add 0x1958440, 0x195d480 [ORD=33] [ID=31]
            0x1958440: i64 = Register %vreg0 [ID=24]
            0x195d480: i64 = Constant<24> [ORD=33] [ID=14]
          0x1958740: i64 = undef [ORD=3] [ID=4]
        0x195fee0: i32,ch = load 0x1958f40:1, 0x195dd60, 0x1958740<LD4[%34]> [ID=43]
          0x195dd60: i64 = add 0x1958440, 0x195dc60 [ORD=37] [ID=32]
            0x1958440: i64 = Register %vreg0 [ID=24]
            0x195dc60: i64 = Constant<8> [ORD=37] [ID=15]
          0x1958740: i64 = undef [ORD=3] [ID=4]
      0x195ffe0: i1 = setcc 0x1960ae0, 0x19607e0, 0x195c780 [ORD=50] [ID=53]
        0x1960ae0: i32,ch = load 0x1958f40:1, 0x195e360, 0x1958740<LD4[%40]> [ID=44]
          0x195e360: i64 = add 0x1958440, 0x195e260 [ORD=43] [ID=33]
            0x1958440: i64 = Register %vreg0 [ID=24]
            0x195e260: i64 = Constant<28> [ORD=43] [ID=16]
          0x1958740: i64 = undef [ORD=3] [ID=4]
        0x19607e0: i32,ch = load 0x1958f40:1, 0x195e760, 0x1958740<LD4[%44]> [ID=45]
          0x195e760: i64 = add 0x1958440, 0x195e660 [ORD=47] [ID=34]
            0x1958440: i64 = Register %vreg0 [ID=24]
            0x195e660: i64 = Constant<12> [ORD=47] [ID=17]
          0x1958740: i64 = undef [ORD=3] [ID=4]
In function: main


Output:

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