Status: fail
Result: fail
Detail | Value |
---|---|
returncode | 1 |
time | 0.110429048538 |
note | Returncode was 1 |
command | /home/daenzer/src/piglit-git/piglit/framework/../bin/shader_runner tests/../generated_tests/spec/glsl-1.10/execution/built-in-functions/vs-op-ne-ivec4-ivec4-using-if.shader_test -auto |
errors_ignored |
|
errors |
|
info | Returncode: 1 Errors: LLVM ERROR: Cannot select: 0xe795d0: i1 = or 0xe796d0, 0xe798d0 [ID=57] 0xe796d0: i1 = or 0xe75b90, 0xe76590 [ID=55] 0xe75b90: i1 = setcc 0xe76090, 0xe76490, 0xe75a90 [ORD=20] [ID=50] 0xe76090: i32,ch = load 0xe4f800:1, 0xe75480, 0xe4f000<LD4[%10]> [ID=38] 0xe75480: i64 = add 0xe797d0, 0xe75380 [ORD=13] [ID=28] 0xe797d0: i64 = Register %vreg0 [ID=24] 0xe75380: i64 = Constant<16> [ORD=13] [ID=10] 0xe4f000: i64 = undef [ORD=3] [ID=4] 0xe76490: i32,ch = load 0xe4f800:1, 0xe797d0, 0xe4f000<LD4[%14]> [ID=39] 0xe797d0: i64 = Register %vreg0 [ID=24] 0xe4f000: i64 = undef [ORD=3] [ID=4] 0xe76590: i1 = setcc 0xe76ba0, 0xe76fa0, 0xe75a90 [ORD=30] [ID=51] 0xe76ba0: i32,ch = load 0xe4f800:1, 0xe75e90, 0xe4f000<LD4[%20]> [ID=40] 0xe75e90: i64 = add 0xe797d0, 0xe75d90 [ORD=23] [ID=29] 0xe797d0: i64 = Register %vreg0 [ID=24] 0xe75d90: i64 = Constant<20> [ORD=23] [ID=12] 0xe4f000: i64 = undef [ORD=3] [ID=4] 0xe76fa0: i32,ch = load 0xe4f800:1, 0xe76290, 0xe4f000<LD4[%24]> [ID=41] 0xe76290: i64 = add 0xe797d0, 0xe76190 [ORD=27] [ID=30] 0xe797d0: i64 = Register %vreg0 [ID=24] 0xe76190: i64 = Constant<4> [ORD=27] [ID=13] 0xe4f000: i64 = undef [ORD=3] [ID=4] 0xe798d0: i1 = or 0xe770a0, 0xe78fd0 [ID=56] 0xe770a0: i1 = setcc 0xe775a0, 0xe78ed0, 0xe75a90 [ORD=40] [ID=52] 0xe775a0: i32,ch = load 0xe4f800:1, 0xe769a0, 0xe4f000<LD4[%30]> [ID=42] 0xe769a0: i64 = add 0xe797d0, 0xe76790 [ORD=33] [ID=31] 0xe797d0: i64 = Register %vreg0 [ID=24] 0xe76790: i64 = Constant<24> [ORD=33] [ID=14] 0xe4f000: i64 = undef [ORD=3] [ID=4] 0xe78ed0: i32,ch = load 0xe4f800:1, 0xe76da0, 0xe4f000<LD4[%34]> [ID=43] 0xe76da0: i64 = add 0xe797d0, 0xe76ca0 [ORD=37] [ID=32] 0xe797d0: i64 = Register %vreg0 [ID=24] 0xe76ca0: i64 = Constant<8> [ORD=37] [ID=15] 0xe4f000: i64 = undef [ORD=3] [ID=4] 0xe78fd0: i1 = setcc 0xe79bd0, 0xe7a1e0, 0xe75a90 [ORD=50] [ID=53] 0xe79bd0: i32,ch = load 0xe4f800:1, 0xe773a0, 0xe4f000<LD4[%40]> [ID=44] 0xe773a0: i64 = add 0xe797d0, 0xe772a0 [ORD=43] [ID=33] 0xe797d0: i64 = Register %vreg0 [ID=24] 0xe772a0: i64 = Constant<28> [ORD=43] [ID=16] 0xe4f000: i64 = undef [ORD=3] [ID=4] 0xe7a1e0: i32,ch = load 0xe4f800:1, 0xe777a0, 0xe4f000<LD4[%44]> [ID=45] 0xe777a0: i64 = add 0xe797d0, 0xe776a0 [ORD=47] [ID=34] 0xe797d0: i64 = Register %vreg0 [ID=24] 0xe776a0: i64 = Constant<12> [ORD=47] [ID=17] 0xe4f000: i64 = undef [ORD=3] [ID=4] In function: main Output: |