brw_draw_upload.c

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00001 /**************************************************************************
00002  *
00003  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
00004  * All Rights Reserved.
00005  *
00006  * Permission is hereby granted, free of charge, to any person obtaining a
00007  * copy of this software and associated documentation files (the
00008  * "Software"), to deal in the Software without restriction, including
00009  * without limitation the rights to use, copy, modify, merge, publish,
00010  * distribute, sub license, and/or sell copies of the Software, and to
00011  * permit persons to whom the Software is furnished to do so, subject to
00012  * the following conditions:
00013  *
00014  * The above copyright notice and this permission notice (including the
00015  * next paragraph) shall be included in all copies or substantial portions
00016  * of the Software.
00017  *
00018  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00019  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00020  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
00021  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
00022  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
00023  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
00024  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
00025  *
00026  **************************************************************************/
00027 
00028 #include <stdlib.h>
00029 
00030 #include "brw_batch.h"
00031 #include "brw_draw.h"
00032 #include "brw_defines.h"
00033 #include "brw_context.h"
00034 #include "brw_state.h"
00035 
00036 
00037 struct brw_array_state {
00038    union header_union header;
00039 
00040    struct {
00041       union {
00042          struct {
00043             unsigned pitch:11;
00044             unsigned pad:15;
00045             unsigned access_type:1;
00046             unsigned vb_index:5;
00047          } bits;
00048          unsigned dword;
00049       } vb0;
00050 
00051       struct pipe_buffer *buffer;
00052       unsigned offset;
00053 
00054       unsigned max_index;
00055       unsigned instance_data_step_rate;
00056 
00057    } vb[BRW_VBP_MAX];
00058 };
00059 
00060 
00061 
00062 unsigned brw_translate_surface_format( unsigned id )
00063 {
00064    switch (id) {
00065    case PIPE_FORMAT_R64_FLOAT:
00066       return BRW_SURFACEFORMAT_R64_FLOAT;
00067    case PIPE_FORMAT_R64G64_FLOAT:
00068       return BRW_SURFACEFORMAT_R64G64_FLOAT;
00069    case PIPE_FORMAT_R64G64B64_FLOAT:
00070       return BRW_SURFACEFORMAT_R64G64B64_FLOAT;
00071    case PIPE_FORMAT_R64G64B64A64_FLOAT:
00072       return BRW_SURFACEFORMAT_R64G64B64A64_FLOAT;
00073 
00074    case PIPE_FORMAT_R32_FLOAT:
00075       return BRW_SURFACEFORMAT_R32_FLOAT;
00076    case PIPE_FORMAT_R32G32_FLOAT:
00077       return BRW_SURFACEFORMAT_R32G32_FLOAT;
00078    case PIPE_FORMAT_R32G32B32_FLOAT:
00079       return BRW_SURFACEFORMAT_R32G32B32_FLOAT;
00080    case PIPE_FORMAT_R32G32B32A32_FLOAT:
00081       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
00082 
00083    case PIPE_FORMAT_R32_UNORM:
00084       return BRW_SURFACEFORMAT_R32_UNORM;
00085    case PIPE_FORMAT_R32G32_UNORM:
00086       return BRW_SURFACEFORMAT_R32G32_UNORM;
00087    case PIPE_FORMAT_R32G32B32_UNORM:
00088       return BRW_SURFACEFORMAT_R32G32B32_UNORM;
00089    case PIPE_FORMAT_R32G32B32A32_UNORM:
00090       return BRW_SURFACEFORMAT_R32G32B32A32_UNORM;
00091 
00092    case PIPE_FORMAT_R32_USCALED:
00093       return BRW_SURFACEFORMAT_R32_USCALED;
00094    case PIPE_FORMAT_R32G32_USCALED:
00095       return BRW_SURFACEFORMAT_R32G32_USCALED;
00096    case PIPE_FORMAT_R32G32B32_USCALED:
00097       return BRW_SURFACEFORMAT_R32G32B32_USCALED;
00098    case PIPE_FORMAT_R32G32B32A32_USCALED:
00099       return BRW_SURFACEFORMAT_R32G32B32A32_USCALED;
00100 
00101    case PIPE_FORMAT_R32_SNORM:
00102       return BRW_SURFACEFORMAT_R32_SNORM;
00103    case PIPE_FORMAT_R32G32_SNORM:
00104       return BRW_SURFACEFORMAT_R32G32_SNORM;
00105    case PIPE_FORMAT_R32G32B32_SNORM:
00106       return BRW_SURFACEFORMAT_R32G32B32_SNORM;
00107    case PIPE_FORMAT_R32G32B32A32_SNORM:
00108       return BRW_SURFACEFORMAT_R32G32B32A32_SNORM;
00109 
00110    case PIPE_FORMAT_R32_SSCALED:
00111       return BRW_SURFACEFORMAT_R32_SSCALED;
00112    case PIPE_FORMAT_R32G32_SSCALED:
00113       return BRW_SURFACEFORMAT_R32G32_SSCALED;
00114    case PIPE_FORMAT_R32G32B32_SSCALED:
00115       return BRW_SURFACEFORMAT_R32G32B32_SSCALED;
00116    case PIPE_FORMAT_R32G32B32A32_SSCALED:
00117       return BRW_SURFACEFORMAT_R32G32B32A32_SSCALED;
00118 
00119    case PIPE_FORMAT_R16_UNORM:
00120       return BRW_SURFACEFORMAT_R16_UNORM;
00121    case PIPE_FORMAT_R16G16_UNORM:
00122       return BRW_SURFACEFORMAT_R16G16_UNORM;
00123    case PIPE_FORMAT_R16G16B16_UNORM:
00124       return BRW_SURFACEFORMAT_R16G16B16_UNORM;
00125    case PIPE_FORMAT_R16G16B16A16_UNORM:
00126       return BRW_SURFACEFORMAT_R16G16B16A16_UNORM;
00127 
00128    case PIPE_FORMAT_R16_USCALED:
00129       return BRW_SURFACEFORMAT_R16_USCALED;
00130    case PIPE_FORMAT_R16G16_USCALED:
00131       return BRW_SURFACEFORMAT_R16G16_USCALED;
00132    case PIPE_FORMAT_R16G16B16_USCALED:
00133       return BRW_SURFACEFORMAT_R16G16B16_USCALED;
00134    case PIPE_FORMAT_R16G16B16A16_USCALED:
00135       return BRW_SURFACEFORMAT_R16G16B16A16_USCALED;
00136 
00137    case PIPE_FORMAT_R16_SNORM:
00138       return BRW_SURFACEFORMAT_R16_SNORM;
00139    case PIPE_FORMAT_R16G16_SNORM:
00140       return BRW_SURFACEFORMAT_R16G16_SNORM;
00141    case PIPE_FORMAT_R16G16B16_SNORM:
00142       return BRW_SURFACEFORMAT_R16G16B16_SNORM;
00143    case PIPE_FORMAT_R16G16B16A16_SNORM:
00144       return BRW_SURFACEFORMAT_R16G16B16A16_SNORM;
00145 
00146    case PIPE_FORMAT_R16_SSCALED:
00147       return BRW_SURFACEFORMAT_R16_SSCALED;
00148    case PIPE_FORMAT_R16G16_SSCALED:
00149       return BRW_SURFACEFORMAT_R16G16_SSCALED;
00150    case PIPE_FORMAT_R16G16B16_SSCALED:
00151       return BRW_SURFACEFORMAT_R16G16B16_SSCALED;
00152    case PIPE_FORMAT_R16G16B16A16_SSCALED:
00153       return BRW_SURFACEFORMAT_R16G16B16A16_SSCALED;
00154 
00155    case PIPE_FORMAT_R8_UNORM:
00156       return BRW_SURFACEFORMAT_R8_UNORM;
00157    case PIPE_FORMAT_R8G8_UNORM:
00158       return BRW_SURFACEFORMAT_R8G8_UNORM;
00159    case PIPE_FORMAT_R8G8B8_UNORM:
00160       return BRW_SURFACEFORMAT_R8G8B8_UNORM;
00161    case PIPE_FORMAT_R8G8B8A8_UNORM:
00162       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
00163 
00164    case PIPE_FORMAT_R8_USCALED:
00165       return BRW_SURFACEFORMAT_R8_USCALED;
00166    case PIPE_FORMAT_R8G8_USCALED:
00167       return BRW_SURFACEFORMAT_R8G8_USCALED;
00168    case PIPE_FORMAT_R8G8B8_USCALED:
00169       return BRW_SURFACEFORMAT_R8G8B8_USCALED;
00170    case PIPE_FORMAT_R8G8B8A8_USCALED:
00171       return BRW_SURFACEFORMAT_R8G8B8A8_USCALED;
00172 
00173    case PIPE_FORMAT_R8_SNORM:
00174       return BRW_SURFACEFORMAT_R8_SNORM;
00175    case PIPE_FORMAT_R8G8_SNORM:
00176       return BRW_SURFACEFORMAT_R8G8_SNORM;
00177    case PIPE_FORMAT_R8G8B8_SNORM:
00178       return BRW_SURFACEFORMAT_R8G8B8_SNORM;
00179    case PIPE_FORMAT_R8G8B8A8_SNORM:
00180       return BRW_SURFACEFORMAT_R8G8B8A8_SNORM;
00181 
00182    case PIPE_FORMAT_R8_SSCALED:
00183       return BRW_SURFACEFORMAT_R8_SSCALED;
00184    case PIPE_FORMAT_R8G8_SSCALED:
00185       return BRW_SURFACEFORMAT_R8G8_SSCALED;
00186    case PIPE_FORMAT_R8G8B8_SSCALED:
00187       return BRW_SURFACEFORMAT_R8G8B8_SSCALED;
00188    case PIPE_FORMAT_R8G8B8A8_SSCALED:
00189       return BRW_SURFACEFORMAT_R8G8B8A8_SSCALED;
00190 
00191    default:
00192       assert(0);
00193       return 0;
00194    }
00195 }
00196 
00197 static unsigned get_index_type(int type)
00198 {
00199    switch (type) {
00200    case 1: return BRW_INDEX_BYTE;
00201    case 2: return BRW_INDEX_WORD;
00202    case 4: return BRW_INDEX_DWORD;
00203    default: assert(0); return 0;
00204    }
00205 }
00206 
00207 
00208 boolean brw_upload_vertex_buffers( struct brw_context *brw )
00209 {
00210    struct brw_array_state vbp;
00211    unsigned nr_enabled = 0;
00212    unsigned i;
00213 
00214    memset(&vbp, 0, sizeof(vbp));
00215 
00216    /* This is a hardware limit:
00217     */
00218 
00219    for (i = 0; i < BRW_VEP_MAX; i++)
00220    {
00221       if (brw->vb.vbo_array[i] == NULL) {
00222          nr_enabled = i;
00223          break;
00224       }
00225 
00226       vbp.vb[i].vb0.bits.pitch = brw->vb.vbo_array[i]->pitch;
00227       vbp.vb[i].vb0.bits.pad = 0;
00228       vbp.vb[i].vb0.bits.access_type = BRW_VERTEXBUFFER_ACCESS_VERTEXDATA;
00229       vbp.vb[i].vb0.bits.vb_index = i;
00230       vbp.vb[i].offset = brw->vb.vbo_array[i]->buffer_offset;
00231       vbp.vb[i].buffer = brw->vb.vbo_array[i]->buffer;
00232       vbp.vb[i].max_index = brw->vb.vbo_array[i]->max_index;
00233    }
00234 
00235 
00236    vbp.header.bits.length = (1 + nr_enabled * 4) - 2;
00237    vbp.header.bits.opcode = CMD_VERTEX_BUFFER;
00238 
00239    BEGIN_BATCH(vbp.header.bits.length+2, 0);
00240    OUT_BATCH( vbp.header.dword );
00241 
00242    for (i = 0; i < nr_enabled; i++) {
00243       OUT_BATCH( vbp.vb[i].vb0.dword );
00244       OUT_RELOC( vbp.vb[i].buffer,  PIPE_BUFFER_USAGE_GPU_READ,
00245                  vbp.vb[i].offset);
00246       OUT_BATCH( vbp.vb[i].max_index );
00247       OUT_BATCH( vbp.vb[i].instance_data_step_rate );
00248    }
00249    ADVANCE_BATCH();
00250    return TRUE;
00251 }
00252 
00253 
00254 
00255 boolean brw_upload_vertex_elements( struct brw_context *brw )
00256 {
00257    struct brw_vertex_element_packet vep;
00258 
00259    unsigned i;
00260    unsigned nr_enabled = brw->attribs.VertexProgram->info.num_inputs;
00261 
00262    memset(&vep, 0, sizeof(vep));
00263 
00264    for (i = 0; i < nr_enabled; i++) 
00265       vep.ve[i] = brw->vb.inputs[i];
00266 
00267 
00268    vep.header.length = (1 + nr_enabled * sizeof(vep.ve[0])/4) - 2;
00269    vep.header.opcode = CMD_VERTEX_ELEMENT;
00270    brw_cached_batch_struct(brw, &vep, 4 + nr_enabled * sizeof(vep.ve[0]));
00271 
00272    return TRUE;
00273 }
00274 
00275 boolean brw_upload_indices( struct brw_context *brw,
00276                             const struct pipe_buffer *index_buffer,
00277                             int ib_size, int start, int count)
00278 {
00279    /* Emit the indexbuffer packet:
00280     */
00281    {
00282       struct brw_indexbuffer ib;
00283 
00284       memset(&ib, 0, sizeof(ib));
00285 
00286       ib.header.bits.opcode = CMD_INDEX_BUFFER;
00287       ib.header.bits.length = sizeof(ib)/4 - 2;
00288       ib.header.bits.index_format = get_index_type(ib_size);
00289       ib.header.bits.cut_index_enable = 0;
00290 
00291 
00292       BEGIN_BATCH(4, 0);
00293       OUT_BATCH( ib.header.dword );
00294       OUT_RELOC( index_buffer, PIPE_BUFFER_USAGE_GPU_READ, start);
00295       OUT_RELOC( index_buffer, PIPE_BUFFER_USAGE_GPU_READ, start + count);
00296       OUT_BATCH( 0 );
00297       ADVANCE_BATCH();
00298    }
00299    return TRUE;
00300 }

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