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Functions | |
void | brw_init_draw_functions (struct brw_context *brw) |
boolean | brw_upload_vertices (struct brw_context *brw, unsigned min_index, unsigned max_index) |
boolean | brw_upload_indices (struct brw_context *brw, const struct pipe_buffer *index_buffer, int ib_size, int start, int count) |
boolean | brw_upload_vertex_buffers (struct brw_context *brw) |
boolean | brw_upload_vertex_elements (struct brw_context *brw) |
unsigned | brw_translate_surface_format (unsigned id) |
void brw_init_draw_functions | ( | struct brw_context * | brw | ) |
Definition at line 233 of file brw_draw.c.
References brw_draw_arrays(), brw_draw_elements(), pipe_context::draw_arrays, pipe_context::draw_elements, and brw_context::pipe.
00234 { 00235 brw->pipe.draw_arrays = brw_draw_arrays; 00236 brw->pipe.draw_elements = brw_draw_elements; 00237 }
unsigned brw_translate_surface_format | ( | unsigned | id | ) |
Definition at line 62 of file brw_draw_upload.c.
References assert, BRW_SURFACEFORMAT_R16_SNORM, BRW_SURFACEFORMAT_R16_SSCALED, BRW_SURFACEFORMAT_R16_UNORM, BRW_SURFACEFORMAT_R16_USCALED, BRW_SURFACEFORMAT_R16G16_SNORM, BRW_SURFACEFORMAT_R16G16_SSCALED, BRW_SURFACEFORMAT_R16G16_UNORM, BRW_SURFACEFORMAT_R16G16_USCALED, BRW_SURFACEFORMAT_R16G16B16_SNORM, BRW_SURFACEFORMAT_R16G16B16_SSCALED, BRW_SURFACEFORMAT_R16G16B16_UNORM, BRW_SURFACEFORMAT_R16G16B16_USCALED, BRW_SURFACEFORMAT_R16G16B16A16_SNORM, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED, BRW_SURFACEFORMAT_R16G16B16A16_UNORM, BRW_SURFACEFORMAT_R16G16B16A16_USCALED, BRW_SURFACEFORMAT_R32_FLOAT, BRW_SURFACEFORMAT_R32_SNORM, BRW_SURFACEFORMAT_R32_SSCALED, BRW_SURFACEFORMAT_R32_UNORM, BRW_SURFACEFORMAT_R32_USCALED, BRW_SURFACEFORMAT_R32G32_FLOAT, BRW_SURFACEFORMAT_R32G32_SNORM, BRW_SURFACEFORMAT_R32G32_SSCALED, BRW_SURFACEFORMAT_R32G32_UNORM, BRW_SURFACEFORMAT_R32G32_USCALED, BRW_SURFACEFORMAT_R32G32B32_FLOAT, BRW_SURFACEFORMAT_R32G32B32_SNORM, BRW_SURFACEFORMAT_R32G32B32_SSCALED, BRW_SURFACEFORMAT_R32G32B32_UNORM, BRW_SURFACEFORMAT_R32G32B32_USCALED, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT, BRW_SURFACEFORMAT_R32G32B32A32_SNORM, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED, BRW_SURFACEFORMAT_R32G32B32A32_UNORM, BRW_SURFACEFORMAT_R32G32B32A32_USCALED, BRW_SURFACEFORMAT_R64_FLOAT, BRW_SURFACEFORMAT_R64G64_FLOAT, BRW_SURFACEFORMAT_R64G64B64_FLOAT, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT, BRW_SURFACEFORMAT_R8_SNORM, BRW_SURFACEFORMAT_R8_SSCALED, BRW_SURFACEFORMAT_R8_UNORM, BRW_SURFACEFORMAT_R8_USCALED, BRW_SURFACEFORMAT_R8G8_SNORM, BRW_SURFACEFORMAT_R8G8_SSCALED, BRW_SURFACEFORMAT_R8G8_UNORM, BRW_SURFACEFORMAT_R8G8_USCALED, BRW_SURFACEFORMAT_R8G8B8_SNORM, BRW_SURFACEFORMAT_R8G8B8_SSCALED, BRW_SURFACEFORMAT_R8G8B8_UNORM, BRW_SURFACEFORMAT_R8G8B8_USCALED, BRW_SURFACEFORMAT_R8G8B8A8_SNORM, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED, BRW_SURFACEFORMAT_R8G8B8A8_UNORM, BRW_SURFACEFORMAT_R8G8B8A8_USCALED, PIPE_FORMAT_R16_SNORM, PIPE_FORMAT_R16_SSCALED, PIPE_FORMAT_R16_UNORM, PIPE_FORMAT_R16_USCALED, PIPE_FORMAT_R16G16_SNORM, PIPE_FORMAT_R16G16_SSCALED, PIPE_FORMAT_R16G16_UNORM, PIPE_FORMAT_R16G16_USCALED, PIPE_FORMAT_R16G16B16_SNORM, PIPE_FORMAT_R16G16B16_SSCALED, PIPE_FORMAT_R16G16B16_UNORM, PIPE_FORMAT_R16G16B16_USCALED, PIPE_FORMAT_R16G16B16A16_SNORM, PIPE_FORMAT_R16G16B16A16_SSCALED, PIPE_FORMAT_R16G16B16A16_UNORM, PIPE_FORMAT_R16G16B16A16_USCALED, PIPE_FORMAT_R32_FLOAT, PIPE_FORMAT_R32_SNORM, PIPE_FORMAT_R32_SSCALED, PIPE_FORMAT_R32_UNORM, PIPE_FORMAT_R32_USCALED, PIPE_FORMAT_R32G32_FLOAT, PIPE_FORMAT_R32G32_SNORM, PIPE_FORMAT_R32G32_SSCALED, PIPE_FORMAT_R32G32_UNORM, PIPE_FORMAT_R32G32_USCALED, PIPE_FORMAT_R32G32B32_FLOAT, PIPE_FORMAT_R32G32B32_SNORM, PIPE_FORMAT_R32G32B32_SSCALED, PIPE_FORMAT_R32G32B32_UNORM, PIPE_FORMAT_R32G32B32_USCALED, PIPE_FORMAT_R32G32B32A32_FLOAT, PIPE_FORMAT_R32G32B32A32_SNORM, PIPE_FORMAT_R32G32B32A32_SSCALED, PIPE_FORMAT_R32G32B32A32_UNORM, PIPE_FORMAT_R32G32B32A32_USCALED, PIPE_FORMAT_R64_FLOAT, PIPE_FORMAT_R64G64_FLOAT, PIPE_FORMAT_R64G64B64_FLOAT, PIPE_FORMAT_R64G64B64A64_FLOAT, PIPE_FORMAT_R8_SNORM, PIPE_FORMAT_R8_SSCALED, PIPE_FORMAT_R8_UNORM, PIPE_FORMAT_R8_USCALED, PIPE_FORMAT_R8G8_SNORM, PIPE_FORMAT_R8G8_SSCALED, PIPE_FORMAT_R8G8_UNORM, PIPE_FORMAT_R8G8_USCALED, PIPE_FORMAT_R8G8B8_SNORM, PIPE_FORMAT_R8G8B8_SSCALED, PIPE_FORMAT_R8G8B8_UNORM, PIPE_FORMAT_R8G8B8_USCALED, PIPE_FORMAT_R8G8B8A8_SNORM, PIPE_FORMAT_R8G8B8A8_SSCALED, PIPE_FORMAT_R8G8B8A8_UNORM, and PIPE_FORMAT_R8G8B8A8_USCALED.
00063 { 00064 switch (id) { 00065 case PIPE_FORMAT_R64_FLOAT: 00066 return BRW_SURFACEFORMAT_R64_FLOAT; 00067 case PIPE_FORMAT_R64G64_FLOAT: 00068 return BRW_SURFACEFORMAT_R64G64_FLOAT; 00069 case PIPE_FORMAT_R64G64B64_FLOAT: 00070 return BRW_SURFACEFORMAT_R64G64B64_FLOAT; 00071 case PIPE_FORMAT_R64G64B64A64_FLOAT: 00072 return BRW_SURFACEFORMAT_R64G64B64A64_FLOAT; 00073 00074 case PIPE_FORMAT_R32_FLOAT: 00075 return BRW_SURFACEFORMAT_R32_FLOAT; 00076 case PIPE_FORMAT_R32G32_FLOAT: 00077 return BRW_SURFACEFORMAT_R32G32_FLOAT; 00078 case PIPE_FORMAT_R32G32B32_FLOAT: 00079 return BRW_SURFACEFORMAT_R32G32B32_FLOAT; 00080 case PIPE_FORMAT_R32G32B32A32_FLOAT: 00081 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT; 00082 00083 case PIPE_FORMAT_R32_UNORM: 00084 return BRW_SURFACEFORMAT_R32_UNORM; 00085 case PIPE_FORMAT_R32G32_UNORM: 00086 return BRW_SURFACEFORMAT_R32G32_UNORM; 00087 case PIPE_FORMAT_R32G32B32_UNORM: 00088 return BRW_SURFACEFORMAT_R32G32B32_UNORM; 00089 case PIPE_FORMAT_R32G32B32A32_UNORM: 00090 return BRW_SURFACEFORMAT_R32G32B32A32_UNORM; 00091 00092 case PIPE_FORMAT_R32_USCALED: 00093 return BRW_SURFACEFORMAT_R32_USCALED; 00094 case PIPE_FORMAT_R32G32_USCALED: 00095 return BRW_SURFACEFORMAT_R32G32_USCALED; 00096 case PIPE_FORMAT_R32G32B32_USCALED: 00097 return BRW_SURFACEFORMAT_R32G32B32_USCALED; 00098 case PIPE_FORMAT_R32G32B32A32_USCALED: 00099 return BRW_SURFACEFORMAT_R32G32B32A32_USCALED; 00100 00101 case PIPE_FORMAT_R32_SNORM: 00102 return BRW_SURFACEFORMAT_R32_SNORM; 00103 case PIPE_FORMAT_R32G32_SNORM: 00104 return BRW_SURFACEFORMAT_R32G32_SNORM; 00105 case PIPE_FORMAT_R32G32B32_SNORM: 00106 return BRW_SURFACEFORMAT_R32G32B32_SNORM; 00107 case PIPE_FORMAT_R32G32B32A32_SNORM: 00108 return BRW_SURFACEFORMAT_R32G32B32A32_SNORM; 00109 00110 case PIPE_FORMAT_R32_SSCALED: 00111 return BRW_SURFACEFORMAT_R32_SSCALED; 00112 case PIPE_FORMAT_R32G32_SSCALED: 00113 return BRW_SURFACEFORMAT_R32G32_SSCALED; 00114 case PIPE_FORMAT_R32G32B32_SSCALED: 00115 return BRW_SURFACEFORMAT_R32G32B32_SSCALED; 00116 case PIPE_FORMAT_R32G32B32A32_SSCALED: 00117 return BRW_SURFACEFORMAT_R32G32B32A32_SSCALED; 00118 00119 case PIPE_FORMAT_R16_UNORM: 00120 return BRW_SURFACEFORMAT_R16_UNORM; 00121 case PIPE_FORMAT_R16G16_UNORM: 00122 return BRW_SURFACEFORMAT_R16G16_UNORM; 00123 case PIPE_FORMAT_R16G16B16_UNORM: 00124 return BRW_SURFACEFORMAT_R16G16B16_UNORM; 00125 case PIPE_FORMAT_R16G16B16A16_UNORM: 00126 return BRW_SURFACEFORMAT_R16G16B16A16_UNORM; 00127 00128 case PIPE_FORMAT_R16_USCALED: 00129 return BRW_SURFACEFORMAT_R16_USCALED; 00130 case PIPE_FORMAT_R16G16_USCALED: 00131 return BRW_SURFACEFORMAT_R16G16_USCALED; 00132 case PIPE_FORMAT_R16G16B16_USCALED: 00133 return BRW_SURFACEFORMAT_R16G16B16_USCALED; 00134 case PIPE_FORMAT_R16G16B16A16_USCALED: 00135 return BRW_SURFACEFORMAT_R16G16B16A16_USCALED; 00136 00137 case PIPE_FORMAT_R16_SNORM: 00138 return BRW_SURFACEFORMAT_R16_SNORM; 00139 case PIPE_FORMAT_R16G16_SNORM: 00140 return BRW_SURFACEFORMAT_R16G16_SNORM; 00141 case PIPE_FORMAT_R16G16B16_SNORM: 00142 return BRW_SURFACEFORMAT_R16G16B16_SNORM; 00143 case PIPE_FORMAT_R16G16B16A16_SNORM: 00144 return BRW_SURFACEFORMAT_R16G16B16A16_SNORM; 00145 00146 case PIPE_FORMAT_R16_SSCALED: 00147 return BRW_SURFACEFORMAT_R16_SSCALED; 00148 case PIPE_FORMAT_R16G16_SSCALED: 00149 return BRW_SURFACEFORMAT_R16G16_SSCALED; 00150 case PIPE_FORMAT_R16G16B16_SSCALED: 00151 return BRW_SURFACEFORMAT_R16G16B16_SSCALED; 00152 case PIPE_FORMAT_R16G16B16A16_SSCALED: 00153 return BRW_SURFACEFORMAT_R16G16B16A16_SSCALED; 00154 00155 case PIPE_FORMAT_R8_UNORM: 00156 return BRW_SURFACEFORMAT_R8_UNORM; 00157 case PIPE_FORMAT_R8G8_UNORM: 00158 return BRW_SURFACEFORMAT_R8G8_UNORM; 00159 case PIPE_FORMAT_R8G8B8_UNORM: 00160 return BRW_SURFACEFORMAT_R8G8B8_UNORM; 00161 case PIPE_FORMAT_R8G8B8A8_UNORM: 00162 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM; 00163 00164 case PIPE_FORMAT_R8_USCALED: 00165 return BRW_SURFACEFORMAT_R8_USCALED; 00166 case PIPE_FORMAT_R8G8_USCALED: 00167 return BRW_SURFACEFORMAT_R8G8_USCALED; 00168 case PIPE_FORMAT_R8G8B8_USCALED: 00169 return BRW_SURFACEFORMAT_R8G8B8_USCALED; 00170 case PIPE_FORMAT_R8G8B8A8_USCALED: 00171 return BRW_SURFACEFORMAT_R8G8B8A8_USCALED; 00172 00173 case PIPE_FORMAT_R8_SNORM: 00174 return BRW_SURFACEFORMAT_R8_SNORM; 00175 case PIPE_FORMAT_R8G8_SNORM: 00176 return BRW_SURFACEFORMAT_R8G8_SNORM; 00177 case PIPE_FORMAT_R8G8B8_SNORM: 00178 return BRW_SURFACEFORMAT_R8G8B8_SNORM; 00179 case PIPE_FORMAT_R8G8B8A8_SNORM: 00180 return BRW_SURFACEFORMAT_R8G8B8A8_SNORM; 00181 00182 case PIPE_FORMAT_R8_SSCALED: 00183 return BRW_SURFACEFORMAT_R8_SSCALED; 00184 case PIPE_FORMAT_R8G8_SSCALED: 00185 return BRW_SURFACEFORMAT_R8G8_SSCALED; 00186 case PIPE_FORMAT_R8G8B8_SSCALED: 00187 return BRW_SURFACEFORMAT_R8G8B8_SSCALED; 00188 case PIPE_FORMAT_R8G8B8A8_SSCALED: 00189 return BRW_SURFACEFORMAT_R8G8B8A8_SSCALED; 00190 00191 default: 00192 assert(0); 00193 return 0; 00194 } 00195 }
boolean brw_upload_indices | ( | struct brw_context * | brw, | |
const struct pipe_buffer * | index_buffer, | |||
int | ib_size, | |||
int | start, | |||
int | count | |||
) |
Definition at line 275 of file brw_draw_upload.c.
References ADVANCE_BATCH, BEGIN_BATCH, brw_indexbuffer::bits, CMD_INDEX_BUFFER, brw_indexbuffer::dword, get_index_type(), brw_indexbuffer::header, OUT_BATCH, OUT_RELOC, PIPE_BUFFER_USAGE_GPU_READ, and TRUE.
00278 { 00279 /* Emit the indexbuffer packet: 00280 */ 00281 { 00282 struct brw_indexbuffer ib; 00283 00284 memset(&ib, 0, sizeof(ib)); 00285 00286 ib.header.bits.opcode = CMD_INDEX_BUFFER; 00287 ib.header.bits.length = sizeof(ib)/4 - 2; 00288 ib.header.bits.index_format = get_index_type(ib_size); 00289 ib.header.bits.cut_index_enable = 0; 00290 00291 00292 BEGIN_BATCH(4, 0); 00293 OUT_BATCH( ib.header.dword ); 00294 OUT_RELOC( index_buffer, PIPE_BUFFER_USAGE_GPU_READ, start); 00295 OUT_RELOC( index_buffer, PIPE_BUFFER_USAGE_GPU_READ, start + count); 00296 OUT_BATCH( 0 ); 00297 ADVANCE_BATCH(); 00298 } 00299 return TRUE; 00300 }
boolean brw_upload_vertex_buffers | ( | struct brw_context * | brw | ) |
Definition at line 208 of file brw_draw_upload.c.
References ADVANCE_BATCH, BEGIN_BATCH, header_union::bits, BRW_VEP_MAX, BRW_VERTEXBUFFER_ACCESS_VERTEXDATA, pipe_vertex_buffer::buffer, brw_array_state::buffer, pipe_vertex_buffer::buffer_offset, CMD_VERTEX_BUFFER, header_union::dword, brw_array_state::header, brw_array_state::instance_data_step_rate, header::length, pipe_vertex_buffer::max_index, brw_array_state::max_index, brw_array_state::offset, header::opcode, OUT_BATCH, OUT_RELOC, PIPE_BUFFER_USAGE_GPU_READ, pipe_vertex_buffer::pitch, TRUE, brw_array_state::vb, brw_context::vb, brw_array_state::vb0, and brw_context::vbo_array.
00209 { 00210 struct brw_array_state vbp; 00211 unsigned nr_enabled = 0; 00212 unsigned i; 00213 00214 memset(&vbp, 0, sizeof(vbp)); 00215 00216 /* This is a hardware limit: 00217 */ 00218 00219 for (i = 0; i < BRW_VEP_MAX; i++) 00220 { 00221 if (brw->vb.vbo_array[i] == NULL) { 00222 nr_enabled = i; 00223 break; 00224 } 00225 00226 vbp.vb[i].vb0.bits.pitch = brw->vb.vbo_array[i]->pitch; 00227 vbp.vb[i].vb0.bits.pad = 0; 00228 vbp.vb[i].vb0.bits.access_type = BRW_VERTEXBUFFER_ACCESS_VERTEXDATA; 00229 vbp.vb[i].vb0.bits.vb_index = i; 00230 vbp.vb[i].offset = brw->vb.vbo_array[i]->buffer_offset; 00231 vbp.vb[i].buffer = brw->vb.vbo_array[i]->buffer; 00232 vbp.vb[i].max_index = brw->vb.vbo_array[i]->max_index; 00233 } 00234 00235 00236 vbp.header.bits.length = (1 + nr_enabled * 4) - 2; 00237 vbp.header.bits.opcode = CMD_VERTEX_BUFFER; 00238 00239 BEGIN_BATCH(vbp.header.bits.length+2, 0); 00240 OUT_BATCH( vbp.header.dword ); 00241 00242 for (i = 0; i < nr_enabled; i++) { 00243 OUT_BATCH( vbp.vb[i].vb0.dword ); 00244 OUT_RELOC( vbp.vb[i].buffer, PIPE_BUFFER_USAGE_GPU_READ, 00245 vbp.vb[i].offset); 00246 OUT_BATCH( vbp.vb[i].max_index ); 00247 OUT_BATCH( vbp.vb[i].instance_data_step_rate ); 00248 } 00249 ADVANCE_BATCH(); 00250 return TRUE; 00251 }
boolean brw_upload_vertex_elements | ( | struct brw_context * | brw | ) |
Definition at line 255 of file brw_draw_upload.c.
References brw_context::attribs, brw_cached_batch_struct(), CMD_VERTEX_ELEMENT, brw_vertex_element_packet::header, brw_vertex_program::info, brw_context::inputs, header::length, tgsi_shader_info::num_inputs, header::opcode, TRUE, brw_context::vb, brw_vertex_element_packet::ve, and brw_context::VertexProgram.
00256 { 00257 struct brw_vertex_element_packet vep; 00258 00259 unsigned i; 00260 unsigned nr_enabled = brw->attribs.VertexProgram->info.num_inputs; 00261 00262 memset(&vep, 0, sizeof(vep)); 00263 00264 for (i = 0; i < nr_enabled; i++) 00265 vep.ve[i] = brw->vb.inputs[i]; 00266 00267 00268 vep.header.length = (1 + nr_enabled * sizeof(vep.ve[0])/4) - 2; 00269 vep.header.opcode = CMD_VERTEX_ELEMENT; 00270 brw_cached_batch_struct(brw, &vep, 4 + nr_enabled * sizeof(vep.ve[0])); 00271 00272 return TRUE; 00273 }
boolean brw_upload_vertices | ( | struct brw_context * | brw, | |
unsigned | min_index, | |||
unsigned | max_index | |||
) |