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00033 #include "brw_context.h"
00034 #include "brw_state.h"
00035 #include "brw_defines.h"
00036 #include "brw_wm.h"
00037 #include "util/u_math.h"
00038 #include "util/u_memory.h"
00039
00040
00041
00042
00043 static void upload_wm_unit(struct brw_context *brw )
00044 {
00045 struct brw_wm_unit_state wm;
00046 unsigned max_threads;
00047 unsigned per_thread;
00048
00049 if (BRW_DEBUG & DEBUG_SINGLE_THREAD)
00050 max_threads = 0;
00051 else
00052 max_threads = 31;
00053
00054
00055 memset(&wm, 0, sizeof(wm));
00056
00057
00058 wm.thread0.grf_reg_count = align(brw->wm.prog_data->total_grf, 16) / 16 - 1;
00059 wm.thread0.kernel_start_pointer = brw->wm.prog_gs_offset >> 6;
00060 wm.thread3.dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf;
00061 wm.thread3.urb_entry_read_length = brw->wm.prog_data->urb_read_length;
00062 wm.thread3.const_urb_entry_read_length = brw->wm.prog_data->curb_read_length;
00063
00064 wm.wm5.max_threads = max_threads;
00065
00066 per_thread = align(brw->wm.prog_data->total_scratch, 1024);
00067 assert(per_thread <= 12 * 1024);
00068
00069 #if 0
00070 if (brw->wm.prog_data->total_scratch) {
00071 unsigned total = per_thread * (max_threads + 1);
00072
00073
00074
00075
00076 brw->wm.scratch_buffer_size = total;
00077 if (brw->wm.scratch_buffer &&
00078 brw->wm.scratch_buffer_size > brw->wm.scratch_buffer->size) {
00079 dri_bo_unreference(brw->wm.scratch_buffer);
00080 brw->wm.scratch_buffer = NULL;
00081 }
00082 if (!brw->wm.scratch_buffer) {
00083 brw->wm.scratch_buffer = dri_bo_alloc(intel->intelScreen->bufmgr,
00084 "wm scratch",
00085 brw->wm.scratch_buffer_size,
00086 4096, DRM_BO_FLAG_MEM_TT);
00087 }
00088 }
00089
00090
00091
00092
00093
00094
00095
00096
00097 assert(brw->wm.prog_data->total_scratch == 0);
00098 #endif
00099
00100
00101 wm.thread1.binding_table_entry_count = brw->wm.nr_surfaces;
00102
00103
00104 wm.thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
00105
00106 wm.thread3.urb_entry_read_offset = 0;
00107 wm.thread1.depth_coef_urb_read_offset = 1;
00108 wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
00109
00110
00111 wm.wm4.sampler_count = (brw->wm.sampler_count + 1) / 4;
00112 wm.wm4.sampler_state_pointer = brw->wm.sampler_gs_offset >> 5;
00113
00114
00115 {
00116 const struct brw_fragment_program *fp = brw->attribs.FragmentProgram;
00117
00118 if (fp->UsesDepth)
00119 wm.wm5.program_uses_depth = 1;
00120
00121 if (fp->info.writes_z)
00122 wm.wm5.program_computes_depth = 1;
00123
00124
00125 if (fp->info.uses_kill ||
00126 brw->attribs.DepthStencil->alpha.enabled)
00127 wm.wm5.program_uses_killpixel = 1;
00128
00129 wm.wm5.enable_8_pix = 1;
00130 }
00131
00132 wm.wm5.thread_dispatch_enable = 1;
00133 wm.wm5.legacy_line_rast = 0;
00134 wm.wm5.legacy_global_depth_bias = 0;
00135 wm.wm5.early_depth_test = 1;
00136 wm.wm5.line_aa_region_width = 0;
00137 wm.wm5.line_endcap_aa_region_width = 1;
00138
00139
00140 if (brw->attribs.Raster->poly_stipple_enable)
00141 wm.wm5.polygon_stipple = 1;
00142
00143 #if 0
00144 if (brw->attribs.Polygon->OffsetFill) {
00145 wm.wm5.depth_offset = 1;
00146
00147
00148
00149
00150
00151 wm.global_depth_offset_constant = brw->attribs.Polygon->OffsetUnits * 2;
00152
00153
00154
00155 wm.global_depth_offset_scale = brw->attribs.Polygon->OffsetFactor;
00156 }
00157 #endif
00158
00159 if (brw->attribs.Raster->line_stipple_enable) {
00160 wm.wm5.line_stipple = 1;
00161 }
00162
00163 if (BRW_DEBUG & DEBUG_STATS)
00164 wm.wm4.stats_enable = 1;
00165
00166 brw->wm.state_gs_offset = brw_cache_data( &brw->cache[BRW_WM_UNIT], &wm );
00167
00168 if (brw->wm.prog_data->total_scratch) {
00169
00170
00171
00172
00173
00174
00175
00176
00177 } else {
00178 wm.thread2.scratch_space_base_pointer = 0;
00179 }
00180 }
00181
00182 const struct brw_tracked_state brw_wm_unit = {
00183 .dirty = {
00184 .brw = (BRW_NEW_RASTERIZER |
00185 BRW_NEW_ALPHA_TEST |
00186 BRW_NEW_FS |
00187 BRW_NEW_CURBE_OFFSETS),
00188
00189 .cache = (CACHE_NEW_SURFACE |
00190 CACHE_NEW_WM_PROG |
00191 CACHE_NEW_SAMPLER)
00192 },
00193 .update = upload_wm_unit
00194 };
00195