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00008 #include "intel_be_device.h"
00009 #include "ws_dri_bufmgr.h"
00010 #include "ws_dri_bufpool.h"
00011 #include "ws_dri_fencemgr.h"
00012
00013 #include "pipe/p_winsys.h"
00014 #include "pipe/p_defines.h"
00015 #include "pipe/p_state.h"
00016 #include "pipe/p_inlines.h"
00017 #include "util/u_memory.h"
00018
00019 #include "i915simple/i915_screen.h"
00020
00021
00022
00023 static INLINE struct intel_be_device *
00024 intel_be_device( struct pipe_winsys *winsys )
00025 {
00026 return (struct intel_be_device *)winsys;
00027 }
00028
00029
00030
00031
00032
00033
00034
00035
00036 static void *intel_be_buffer_map(struct pipe_winsys *winsys,
00037 struct pipe_buffer *buf,
00038 unsigned flags )
00039 {
00040 unsigned drm_flags = 0;
00041
00042 if (flags & PIPE_BUFFER_USAGE_CPU_WRITE)
00043 drm_flags |= DRM_BO_FLAG_WRITE;
00044
00045 if (flags & PIPE_BUFFER_USAGE_CPU_READ)
00046 drm_flags |= DRM_BO_FLAG_READ;
00047
00048 return driBOMap( dri_bo(buf), drm_flags, 0 );
00049 }
00050
00051 static void intel_be_buffer_unmap(struct pipe_winsys *winsys,
00052 struct pipe_buffer *buf)
00053 {
00054 driBOUnmap( dri_bo(buf) );
00055 }
00056
00057 static void
00058 intel_be_buffer_destroy(struct pipe_winsys *winsys,
00059 struct pipe_buffer *buf)
00060 {
00061 driBOUnReference( dri_bo(buf) );
00062 FREE(buf);
00063 }
00064
00065 static struct pipe_buffer *
00066 intel_be_buffer_create(struct pipe_winsys *winsys,
00067 unsigned alignment,
00068 unsigned usage,
00069 unsigned size )
00070 {
00071 struct intel_be_buffer *buffer = CALLOC_STRUCT( intel_be_buffer );
00072 struct intel_be_device *iws = intel_be_device(winsys);
00073 unsigned flags = 0;
00074 struct _DriBufferPool *pool;
00075
00076 buffer->base.refcount = 1;
00077 buffer->base.alignment = alignment;
00078 buffer->base.usage = usage;
00079 buffer->base.size = size;
00080
00081 if (usage & (PIPE_BUFFER_USAGE_VERTEX | PIPE_BUFFER_USAGE_CONSTANT)) {
00082 flags |= DRM_BO_FLAG_MEM_LOCAL | DRM_BO_FLAG_CACHED;
00083 pool = iws->mallocPool;
00084 } else if (usage & PIPE_BUFFER_USAGE_CUSTOM) {
00085
00086 flags |= DRM_BO_FLAG_MEM_VRAM | DRM_BO_FLAG_MEM_TT;
00087 pool = iws->vertexPool;
00088 } else {
00089 flags |= DRM_BO_FLAG_MEM_VRAM | DRM_BO_FLAG_MEM_TT;
00090 pool = iws->regionPool;
00091 }
00092
00093 if (usage & PIPE_BUFFER_USAGE_GPU_READ)
00094 flags |= DRM_BO_FLAG_READ;
00095
00096 if (usage & PIPE_BUFFER_USAGE_GPU_WRITE)
00097 flags |= DRM_BO_FLAG_WRITE;
00098
00099
00100
00101 if ((flags & (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE)) == 0)
00102 flags |= DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE;
00103
00104 buffer->pool = pool;
00105 driGenBuffers( buffer->pool,
00106 "pipe buffer", 1, &buffer->driBO, alignment, flags, 0 );
00107
00108 driBOData( buffer->driBO, size, NULL, buffer->pool, 0 );
00109
00110 return &buffer->base;
00111 }
00112
00113
00114 static struct pipe_buffer *
00115 intel_be_user_buffer_create(struct pipe_winsys *winsys, void *ptr, unsigned bytes)
00116 {
00117 struct intel_be_buffer *buffer = CALLOC_STRUCT( intel_be_buffer );
00118 struct intel_be_device *iws = intel_be_device(winsys);
00119
00120 driGenUserBuffer( iws->regionPool,
00121 "pipe user buffer", &buffer->driBO, ptr, bytes );
00122
00123 buffer->base.refcount = 1;
00124
00125 return &buffer->base;
00126 }
00127
00128 struct pipe_buffer *
00129 intel_be_buffer_from_handle(struct intel_be_device *device,
00130 const char* name, unsigned handle)
00131 {
00132 struct intel_be_buffer *be_buf = malloc(sizeof(*be_buf));
00133 struct pipe_buffer *buffer;
00134
00135 if (!be_buf)
00136 goto err;
00137
00138 memset(be_buf, 0, sizeof(*be_buf));
00139
00140 driGenBuffers(device->staticPool, name, 1, &be_buf->driBO, 0, 0, 0);
00141 driBOSetReferenced(be_buf->driBO, handle);
00142
00143 if (0)
00144 goto err_bo;
00145
00146 buffer = &be_buf->base;
00147 buffer->refcount = 1;
00148 buffer->alignment = 0;
00149 buffer->usage = 0;
00150 buffer->size = driBOSize(be_buf->driBO);
00151
00152 return buffer;
00153 err_bo:
00154 free(be_buf);
00155 err:
00156 return NULL;
00157 }
00158
00159
00160
00161
00162
00163
00164
00165
00166 static struct pipe_surface *
00167 intel_i915_surface_alloc(struct pipe_winsys *winsys)
00168 {
00169 assert((size_t)"intel_i915_surface_alloc is deprecated" & 0);
00170 return NULL;
00171 }
00172
00173 static int
00174 intel_i915_surface_alloc_storage(struct pipe_winsys *winsys,
00175 struct pipe_surface *surf,
00176 unsigned width, unsigned height,
00177 enum pipe_format format,
00178 unsigned flags,
00179 unsigned tex_usage)
00180 {
00181 assert((size_t)"intel_i915_surface_alloc_storage is deprecated" & 0);
00182 return -1;
00183 }
00184
00185 static void
00186 intel_i915_surface_release(struct pipe_winsys *winsys, struct pipe_surface **s)
00187 {
00188 assert((size_t)"intel_i915_surface_release is deprecated" & 0);
00189 }
00190
00191
00192
00193
00194
00195
00196 static void
00197 intel_be_fence_reference( struct pipe_winsys *sws,
00198 struct pipe_fence_handle **ptr,
00199 struct pipe_fence_handle *fence )
00200 {
00201 if (*ptr)
00202 driFenceUnReference((struct _DriFenceObject **)ptr);
00203
00204 if (fence)
00205 *ptr = (struct pipe_fence_handle *)driFenceReference((struct _DriFenceObject *)fence);
00206 }
00207
00208 static int
00209 intel_be_fence_signalled( struct pipe_winsys *sws,
00210 struct pipe_fence_handle *fence,
00211 unsigned flag )
00212 {
00213 return driFenceSignaled((struct _DriFenceObject *)fence, flag);
00214 }
00215
00216 static int
00217 intel_be_fence_finish( struct pipe_winsys *sws,
00218 struct pipe_fence_handle *fence,
00219 unsigned flag )
00220 {
00221 return driFenceFinish((struct _DriFenceObject *)fence, flag, 0);
00222 }
00223
00224
00225
00226
00227
00228
00229 boolean
00230 intel_be_init_device(struct intel_be_device *dev, int fd, unsigned id)
00231 {
00232 dev->fd = fd;
00233 dev->max_batch_size = 16 * 4096;
00234 dev->max_vertex_size = 128 * 4096;
00235
00236 dev->base.buffer_create = intel_be_buffer_create;
00237 dev->base.user_buffer_create = intel_be_user_buffer_create;
00238 dev->base.buffer_map = intel_be_buffer_map;
00239 dev->base.buffer_unmap = intel_be_buffer_unmap;
00240 dev->base.buffer_destroy = intel_be_buffer_destroy;
00241 dev->base.surface_alloc = intel_i915_surface_alloc;
00242 dev->base.surface_alloc_storage = intel_i915_surface_alloc_storage;
00243 dev->base.surface_release = intel_i915_surface_release;
00244 dev->base.fence_reference = intel_be_fence_reference;
00245 dev->base.fence_signalled = intel_be_fence_signalled;
00246 dev->base.fence_finish = intel_be_fence_finish;
00247
00248 #if 0
00249 dev->base.flush_frontbuffer = intel_flush_frontbuffer;
00250 dev->base.get_name = intel_get_name;
00251 #endif
00252
00253 dev->fMan = driInitFreeSlabManager(10, 10);
00254 dev->fenceMgr = driFenceMgrTTMInit(dev->fd);
00255
00256 dev->mallocPool = driMallocPoolInit();
00257 dev->staticPool = driDRMPoolInit(dev->fd);
00258
00259 dev->regionPool = driSlabPoolInit(dev->fd,
00260 DRM_BO_FLAG_READ |
00261 DRM_BO_FLAG_WRITE |
00262 DRM_BO_FLAG_MEM_TT,
00263 DRM_BO_FLAG_READ |
00264 DRM_BO_FLAG_WRITE |
00265 DRM_BO_FLAG_MEM_TT,
00266 64,
00267 10, 120, 4096 * 64, 0,
00268 dev->fMan);
00269
00270 dev->vertexPool = driSlabPoolInit(dev->fd,
00271 DRM_BO_FLAG_READ |
00272 DRM_BO_FLAG_WRITE |
00273 DRM_BO_FLAG_MEM_TT,
00274 DRM_BO_FLAG_READ |
00275 DRM_BO_FLAG_WRITE |
00276 DRM_BO_FLAG_MEM_TT,
00277 dev->max_vertex_size,
00278 1, 120, dev->max_vertex_size * 4, 0,
00279 dev->fMan);
00280
00281 dev->batchPool = driSlabPoolInit(dev->fd,
00282 DRM_BO_FLAG_EXE |
00283 DRM_BO_FLAG_MEM_TT,
00284 DRM_BO_FLAG_EXE |
00285 DRM_BO_FLAG_MEM_TT,
00286 dev->max_batch_size,
00287 1, 40, dev->max_batch_size * 16, 0,
00288 dev->fMan);
00289
00290
00291
00292
00293 dev->screen = i915_create_screen(&dev->base, id);
00294
00295 return true;
00296 }
00297
00298 void
00299 intel_be_destroy_device(struct intel_be_device *dev)
00300 {
00301 driPoolTakeDown(dev->mallocPool);
00302 driPoolTakeDown(dev->staticPool);
00303 driPoolTakeDown(dev->regionPool);
00304 driPoolTakeDown(dev->vertexPool);
00305 driPoolTakeDown(dev->batchPool);
00306
00308 }