cell_gen_fragment.h File Reference

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Functions
void	cell_gen_fragment_function (struct cell_context *cell, struct spe_function *f)
	Generate SPE code to implement the fragment operations (alpha test, depth test, stencil test, blending, colormask, and final framebuffer write) as specified by the current context state.

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Function Documentation

void cell_gen_fragment_function	(	struct cell_context *	cell,
		struct spe_function *	f
	)

Generate SPE code to implement the fragment operations (alpha test, depth test, stencil test, blending, colormask, and final framebuffer write) as specified by the current context state.

Logically, this code will be called after running the fragment shader. But under some circumstances we could run some of this code before the fragment shader to cull fragments/quads that are totally occluded/discarded.

XXX we only support PIPE_FORMAT_Z24S8_UNORM z/stencil buffer right now.

See the spu_default_fragment_ops() function to see how the per-fragment operations would be done with ordinary C code. The code we generate here though has no branches, is SIMD, etc and should be much faster.

Parameters:

	cell	the rendering context (in)
	f	the generated function (out)

< framebuffer's RGBA colors for quad

< framebuffer's combined z/stencil values for quad

Definition at line 627 of file cell_gen_fragment.c.

References pipe_depth_stencil_alpha_state::alpha, ASSERT, cell_blend_state::base, cell_depth_stencil_alpha_state::base, cell_context::blend, pipe_blend_state::blend_enable, pipe_framebuffer_state::cbufs, pipe_blend_state::colormask, pipe_depth_stencil_alpha_state::depth, cell_context::depth_stencil, pipe_stencil_state::enabled, pipe_depth_state::enabled, pipe_alpha_state::enabled, pipe_surface::format, cell_context::framebuffer, gen_alpha_test(), gen_blend(), gen_colormask(), gen_depth_test(), gen_logicop(), gen_pack_colors(), pipe_blend_state::logicop_enable, PIPE_FORMAT_S8_UNORM, PIPE_FORMAT_S8Z24_UNORM, PIPE_FORMAT_X8Z24_UNORM, PIPE_FORMAT_Z16_UNORM, PIPE_FORMAT_Z24S8_UNORM, PIPE_FORMAT_Z24X8_UNORM, spe_a(), spe_allocate_available_register(), spe_allocate_register(), spe_and(), spe_bi(), spe_cfltu(), spe_fm(), spe_fsmbi(), spe_init_func(), SPE_INST_SIZE, spe_load_float(), spe_lqx(), spe_or(), SPE_REG_RA, spe_release_register(), spe_rotmi(), spe_selb(), spe_shli(), spe_stqx(), SPU_MAX_FRAGMENT_OPS_INSTS, pipe_depth_stencil_alpha_state::stencil, TILE_SIZE, pipe_stencil_state::write_mask, pipe_depth_state::writemask, and pipe_framebuffer_state::zsbuf.

{
   const struct pipe_depth_stencil_alpha_state *dsa =
      &cell->depth_stencil->base;
   const struct pipe_blend_state *blend = &cell->blend->base;
   const enum pipe_format color_format = cell->framebuffer.cbufs[0]->format;

   /* For SPE function calls: reg $3 = first param, $4 = second param, etc. */
   const int x_reg = 3;  /* uint */
   const int y_reg = 4;  /* uint */
   const int color_tile_reg = 5;  /* tile_t * */
   const int depth_tile_reg = 6;  /* tile_t * */
   const int fragZ_reg = 7;   /* vector float */
   const int fragR_reg = 8;   /* vector float */
   const int fragG_reg = 9;   /* vector float */
   const int fragB_reg = 10;  /* vector float */
   const int fragA_reg = 11;  /* vector float */
   const int mask_reg = 12;   /* vector uint */

   /* offset of quad from start of tile
    * XXX assuming 4-byte pixels for color AND Z/stencil!!!!
    */
   int quad_offset_reg;

   int fbRGBA_reg;  
   int fbZS_reg;    
   spe_init_func(f, SPU_MAX_FRAGMENT_OPS_INSTS * SPE_INST_SIZE);
   spe_allocate_register(f, x_reg);
   spe_allocate_register(f, y_reg);
   spe_allocate_register(f, color_tile_reg);
   spe_allocate_register(f, depth_tile_reg);
   spe_allocate_register(f, fragZ_reg);
   spe_allocate_register(f, fragR_reg);
   spe_allocate_register(f, fragG_reg);
   spe_allocate_register(f, fragB_reg);
   spe_allocate_register(f, fragA_reg);
   spe_allocate_register(f, mask_reg);

   quad_offset_reg = spe_allocate_available_register(f);
   fbRGBA_reg = spe_allocate_available_register(f);
   fbZS_reg = spe_allocate_available_register(f);

   /* compute offset of quad from start of tile, in bytes */
   {
      int x2_reg = spe_allocate_available_register(f);
      int y2_reg = spe_allocate_available_register(f);

      ASSERT(TILE_SIZE == 32);

      spe_rotmi(f, x2_reg, x_reg, -1);  /* x2 = x / 2 */
      spe_rotmi(f, y2_reg, y_reg, -1);  /* y2 = y / 2 */
      spe_shli(f, y2_reg, y2_reg, 4);   /* y2 *= 16 */
      spe_a(f, quad_offset_reg, y2_reg, x2_reg);  /* offset = y2 + x2 */
      spe_shli(f, quad_offset_reg, quad_offset_reg, 4);   /* offset *= 16 */

      spe_release_register(f, x2_reg);
      spe_release_register(f, y2_reg);
   }


   if (dsa->alpha.enabled) {
      gen_alpha_test(dsa, f, mask_reg, fragA_reg);
   }

   if (dsa->depth.enabled || dsa->stencil[0].enabled) {
      const enum pipe_format zs_format = cell->framebuffer.zsbuf->format;
      boolean write_depth_stencil;

      int fbZ_reg = spe_allocate_available_register(f); /* Z values */
      int fbS_reg = spe_allocate_available_register(f); /* Stencil values */

      /* fetch quad of depth/stencil values from tile at (x,y) */
      /* Load: fbZS_reg = memory[depth_tile_reg + offset_reg] */
      spe_lqx(f, fbZS_reg, depth_tile_reg, quad_offset_reg);

      if (dsa->depth.enabled) {
         /* Extract Z bits from fbZS_reg into fbZ_reg */
         if (zs_format == PIPE_FORMAT_S8Z24_UNORM ||
             zs_format == PIPE_FORMAT_X8Z24_UNORM) {
            int mask_reg = spe_allocate_available_register(f);
            spe_fsmbi(f, mask_reg, 0x7777);  /* mask[0,1,2,3] = 0x00ffffff */
            spe_and(f, fbZ_reg, fbZS_reg, mask_reg);  /* fbZ = fbZS & mask */
            spe_release_register(f, mask_reg);
            /* OK, fbZ_reg has four 24-bit Z values now */
         }
         else {
            /* XXX handle other z/stencil formats */
            ASSERT(0);
         }

         /* Convert fragZ values from float[4] to uint[4] */
         if (zs_format == PIPE_FORMAT_S8Z24_UNORM ||
             zs_format == PIPE_FORMAT_X8Z24_UNORM ||
             zs_format == PIPE_FORMAT_Z24S8_UNORM ||
             zs_format == PIPE_FORMAT_Z24X8_UNORM) {
            /* 24-bit Z values */
            int scale_reg = spe_allocate_available_register(f);

            /* scale_reg[0,1,2,3] = float(2^24-1) */
            spe_load_float(f, scale_reg, (float) 0xffffff);

            /* XXX these two instructions might be combined */
            spe_fm(f, fragZ_reg, fragZ_reg, scale_reg); /* fragZ *= scale */
            spe_cfltu(f, fragZ_reg, fragZ_reg, 0);  /* fragZ = (int) fragZ */

            spe_release_register(f, scale_reg);
         }
         else {
            /* XXX handle 16-bit Z format */
            ASSERT(0);
         }
      }

      if (dsa->stencil[0].enabled) {
         /* Extract Stencil bit sfrom fbZS_reg into fbS_reg */
         if (zs_format == PIPE_FORMAT_S8Z24_UNORM ||
             zs_format == PIPE_FORMAT_X8Z24_UNORM) {
            /* XXX extract with a shift */
            ASSERT(0);
         }
         else if (zs_format == PIPE_FORMAT_Z24S8_UNORM ||
                  zs_format == PIPE_FORMAT_Z24X8_UNORM) {
            /* XXX extract with a mask */
            ASSERT(0);
         }
      }


      if (dsa->stencil[0].enabled) {
         /* XXX this may involve depth testing too */
         // gen_stencil_test(dsa, f, ... );
         ASSERT(0);
      }
      else if (dsa->depth.enabled) {
         int zmask_reg = spe_allocate_available_register(f);
         gen_depth_test(dsa, f, mask_reg, fragZ_reg, fbZ_reg, zmask_reg);
         spe_release_register(f, zmask_reg);
      }

      /* do we need to write Z and/or Stencil back into framebuffer? */
      write_depth_stencil = (dsa->depth.writemask |
                             dsa->stencil[0].write_mask |
                             dsa->stencil[1].write_mask);

      if (write_depth_stencil) {
         /* Merge latest Z and Stencil values into fbZS_reg.
          * fbZ_reg has four Z vals in bits [23..0] or bits [15..0].
          * fbS_reg has four 8-bit Z values in bits [7..0].
          */
         if (zs_format == PIPE_FORMAT_S8Z24_UNORM ||
             zs_format == PIPE_FORMAT_X8Z24_UNORM) {
            spe_shli(f, fbS_reg, fbS_reg, 24); /* fbS = fbS << 24 */
            spe_or(f, fbZS_reg, fbS_reg, fbZ_reg); /* fbZS = fbS | fbZ */
         }
         else if (zs_format == PIPE_FORMAT_S8Z24_UNORM ||
                  zs_format == PIPE_FORMAT_X8Z24_UNORM) {
            /* XXX to do */
            ASSERT(0);
         }
         else if (zs_format == PIPE_FORMAT_Z16_UNORM) {
            /* XXX to do */
            ASSERT(0);
         }
         else if (zs_format == PIPE_FORMAT_S8_UNORM) {
            /* XXX to do */
            ASSERT(0);
         }
         else {
            /* bad zs_format */
            ASSERT(0);
         }

         /* Store: memory[depth_tile_reg + quad_offset_reg] = fbZS */
         spe_stqx(f, fbZS_reg, depth_tile_reg, quad_offset_reg);
      }

      spe_release_register(f, fbZ_reg);
      spe_release_register(f, fbS_reg);
   }


   /* Get framebuffer quad/colors.  We'll need these for blending,
    * color masking, and to obey the quad/pixel mask.
    * Load: fbRGBA_reg = memory[color_tile + quad_offset]
    * Note: if mask={~0,~0,~0,~0} and we're not blending or colormasking
    * we could skip this load.
    */
   spe_lqx(f, fbRGBA_reg, color_tile_reg, quad_offset_reg);


   if (blend->blend_enable) {
      gen_blend(blend, f, color_format,
                fragR_reg, fragG_reg, fragB_reg, fragA_reg, fbRGBA_reg);
   }

   /*
    * Write fragment colors to framebuffer/tile.
    * This involves converting the fragment colors from float[4] to the
    * tile's specific format and obeying the quad/pixel mask.
    */
   {
      int rgba_reg = spe_allocate_available_register(f);

      /* Pack four float colors as four 32-bit int colors */
      gen_pack_colors(f, color_format,
                      fragR_reg, fragG_reg, fragB_reg, fragA_reg,
                      rgba_reg);

      if (blend->logicop_enable) {
         gen_logicop(blend, f, rgba_reg, fbRGBA_reg);
      }

      if (blend->colormask != 0xf) {
         gen_colormask(blend->colormask, f, rgba_reg, fbRGBA_reg);
      }


      /* Mix fragment colors with framebuffer colors using the quad/pixel mask:
       * if (mask[i])
       *    rgba[i] = rgba[i];
       * else
       *    rgba[i] = framebuffer[i];
       */
      spe_selb(f, rgba_reg, fbRGBA_reg, rgba_reg, mask_reg);

      /* Store updated quad in tile:
       * memory[color_tile + quad_offset] = rgba_reg;
       */
      spe_stqx(f, rgba_reg, color_tile_reg, quad_offset_reg);

      spe_release_register(f, rgba_reg);
   }

   //printf("gen_fragment_ops nr instructions: %u\n", f->num_inst);

   spe_bi(f, SPE_REG_RA, 0, 0);  /* return from function call */


   spe_release_register(f, fbRGBA_reg);
   spe_release_register(f, fbZS_reg);
   spe_release_register(f, quad_offset_reg);
}

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