drm/komeda Arm display driver

The drm/komeda driver supports the Arm display processor D71 and later products, this document gives a brief overview of driver design: how it works and why design it like that.

Overview of D71 like display IPs

From D71, Arm display IP begins to adopt a flexible and modularized architecture. A display pipeline is made up of multiple individual and functional pipeline stages called components, and every component has some specific capabilities that can give the flowed pipeline pixel data a particular processing.

Typical D71 components:


Layer is the first pipeline stage, which prepares the pixel data for the next stage. It fetches the pixel from memory, decodes it if it’s AFBC, rotates the source image, unpacks or converts YUV pixels to the device internal RGB pixels, then adjusts the color_space of pixels if needed.


As its name suggests, scaler takes responsibility for scaling, and D71 also supports image enhancements by scaler. The usage of scaler is very flexible and can be connected to layer output for layer scaling, or connected to compositor and scale the whole display frame and then feed the output data into wb_layer which will then write it into memory.

Compositor (compiz)

Compositor blends multiple layers or pixel data flows into one single display frame. its output frame can be fed into post image processor for showing it on the monitor or fed into wb_layer and written to memory at the same time. user can also insert a scaler between compositor and wb_layer to down scale the display frame first and and then write to memory.

Writeback Layer (wb_layer)

Writeback layer does the opposite things of Layer, which connects to compiz and writes the composition result to memory.

Post image processor (improc)

Post image processor adjusts frame data like gamma and color space to fit the requirements of the monitor.

Timing controller (timing_ctrlr)

Final stage of display pipeline, Timing controller is not for the pixel handling, but only for controlling the display timing.


D71 scaler mostly only has the half horizontal input/output capabilities compared with Layer, like if Layer supports 4K input size, the scaler only can support 2K input/output in the same time. To achieve the ful frame scaling, D71 introduces Layer Split, which splits the whole image to two half parts and feeds them to two Layers A and B, and does the scaling independently. After scaling the result need to be fed to merger to merge two part images together, and then output merged result to compiz.


Similar to Layer Split, but Splitter is used for writeback, which splits the compiz result to two parts and then feed them to two scalers.

Possible D71 Pipeline usage

Benefitting from the modularized architecture, D71 pipelines can be easily adjusted to fit different usages. And D71 has two pipelines, which support two types of working mode:

  • Dual display mode Two pipelines work independently and separately to drive two display outputs.

  • Single display mode Two pipelines work together to drive only one display output.

    On this mode, pipeline_B doesn’t work indenpendently, but outputs its composition result into pipeline_A, and its pixel timing also derived from pipeline_A.timing_ctrlr. The pipeline_B works just like a “slave” of pipeline_A(master)

Single pipeline data flow

Single pipeline digraph

Single pipeline data flow

Dual pipeline with Slave enabled

Slave pipeline digraph

Slave pipeline enabled data flow

Sub-pipelines for input and output

A complete display pipeline can be easily divided into three sub-pipelines according to the in/out usage.

Layer(input) pipeline

Layer data digraph

Layer (input) data flow

Layer Split digraph

Layer Split pipeline

Writeback(output) pipeline

writeback digraph

Writeback(output) data flow

split writeback digraph

Writeback(output) Split data flow

Display output pipeline

display digraph

display output data flow

In the following section we’ll see these three sub-pipelines will be handled by KMS-plane/wb_conn/crtc respectively.

Komeda Resource abstraction

struct komeda_pipeline/component

To fully utilize and easily access/configure the HW, the driver side also uses a similar architecture: Pipeline/Component to describe the HW features and capabilities, and a specific component includes two parts:

  • Data flow controlling.
  • Specific component capabilities and features.

So the driver defines a common header struct komeda_component to describe the data flow control and all specific components are a subclass of this base structure.

struct komeda_component


struct komeda_component {
  struct drm_private_obj obj;
  struct komeda_pipeline *pipeline;
  char name[32];
  u32 __iomem *reg;
  u32 id;
  u32 hw_id;
  u8 max_active_inputs;
  u8 max_active_outputs;
  u32 supported_inputs;
  u32 supported_outputs;
  struct komeda_component_funcs *funcs;


treat component as private obj
the komeda pipeline this component belongs to
component name
component register base, which is initialized by chip and used by chip only
component id


maximum number of inputs/outputs that can be active in the same time Note: the number isn’t the bit number of supported_inputs or supported_outputs, but may be less than it, since component may not support enabling all supported_inputs/outputs at the same time.



bitmask of BIT(component->id) for the supported inputs/outputs describes the possibilities of how a component is linked into a pipeline.

chip functions to access HW


struct komeda_component describe the data flow capabilities for how to link a component into the display pipeline. all specified components are subclass of this structure.

struct komeda_component_output


struct komeda_component_output {
  struct komeda_component *component;
  u8 output_port;


indicate which component the data comes from


a component has multiple outputs, if want to know where the data comes from, only know the component is not enough, we still need to know its output port

struct komeda_component_state


struct komeda_component_state {
  struct drm_private_state obj;
  struct komeda_component *component;
  union {
    struct drm_crtc *crtc;
    struct drm_plane *plane;
    struct drm_connector *wb_conn;
    void *binding_user;
  u16 active_inputs;
  u16 changed_active_inputs;
  u16 affected_inputs;
  struct komeda_component_output inputs[KOMEDA_COMPONENT_N_INPUTS];


tracking component_state by drm_atomic_state

currently bound user, the user can be crtc/plane/wb_conn, which is valid decided by component and inputs

  • Layer: its user always is plane.
  • compiz/improc/timing_ctrlr: the user is crtc.
  • wb_layer: wb_conn;
  • scaler: plane when input is layer, wb_conn if input is compiz.

active_inputs is bitmask of inputs index

  • active_inputs = changed_active_inputs + unchanged_active_inputs
  • affected_inputs = old->active_inputs + new->active_inputs;
  • disabling_inputs = affected_inputs ^ active_inputs;
  • changed_inputs = disabling_inputs + changed_active_inputs;

NOTE: changed_inputs doesn’t include all active_input but only changed_active_inputs, and this bitmask can be used in chip level for dirty update.

the specific inputs[i] only valid on BIT(i) has been set in active_inputs, if not the inputs[i] is undefined.


component_state is the data flow configuration of the component, and it’s the superclass of all specific component_state like komeda_layer_state, komeda_scaler_state

struct komeda_pipeline


struct komeda_pipeline {
  struct drm_private_obj obj;
  struct komeda_dev *mdev;
  struct clk *pxlclk;
  struct clk *aclk;
  int id;
  u32 avail_comps;
  int n_layers;
  struct komeda_layer *layers[KOMEDA_PIPELINE_MAX_LAYERS];
  int n_scalers;
  struct komeda_scaler *scalers[KOMEDA_PIPELINE_MAX_SCALERS];
  struct komeda_compiz *compiz;
  struct komeda_layer  *wb_layer;
  struct komeda_improc *improc;
  struct komeda_timing_ctrlr *ctrlr;
  struct komeda_pipeline_funcs *funcs;
  struct device_node *of_node;
  struct device_node *of_output_port;
  struct device_node *of_output_dev;


link pipeline as private obj of drm_atomic_state
the parent komeda_dev
pixel clock
AXI clock
pipeline id
available components mask of pipeline
pipeline dt node
pipeline output port
output connector device node


Represent a complete display pipeline and hold all functional components.

struct komeda_pipeline_state


struct komeda_pipeline_state {
  struct drm_private_state obj;
  struct komeda_pipeline *pipe;
  struct drm_crtc *crtc;
  u32 active_comps;


tracking pipeline_state by drm_atomic_state
currently bound crtc
bitmask - BIT(component->id) of active components


Unlike the pipeline, pipeline_state doesn’t gather any component_state into it. It because all component will be managed by drm_atomic_state.

Resource discovery and initialization

Pipeline and component are used to describe how to handle the pixel data. We still need a @struct komeda_dev to describe the whole view of the device, and the control-abilites of device.

We have &komeda_dev, &komeda_pipeline, &komeda_component. Now fill devices with pipelines. Since komeda is not for D71 only but also intended for later products, of course we’d better share as much as possible between different products. To achieve this, split the komeda device into two layers: CORE and CHIP.

  • CORE: for common features and capabilities handling.
  • CHIP: for register programing and HW specific feature (limitation) handling.

CORE can access CHIP by three chip function structures:

  • struct komeda_dev_funcs
  • struct komeda_pipeline_funcs
  • struct komeda_component_funcs
struct komeda_dev_funcs


struct komeda_dev_funcs {
  void (*init_format_table)(struct komeda_dev *mdev);
  int (*enum_resources)(struct komeda_dev *mdev);
  void (*cleanup)(struct komeda_dev *mdev);
  irqreturn_t (*irq_handler)(struct komeda_dev *mdev, struct komeda_events *events);
  int (*enable_irq)(struct komeda_dev *mdev);
  int (*disable_irq)(struct komeda_dev *mdev);
  void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq);


initialize komeda_dev->format_table, this function should be called before the enum_resource
for CHIP to report or add pipeline and component resources to CORE
call to chip to cleanup komeda_dev->chip data
for CORE to get the HW event from the CHIP when interrupt happened.
enable irq
disable irq
Optional, dump registers to seq_file


Supplied by chip level and returned by the chip entry function xxx_identify,

struct komeda_dev


struct komeda_dev {
  struct device *dev;
  u32 __iomem   *reg_base;
  struct komeda_chip_info chip;
  struct komeda_format_caps_table fmt_tbl;
  struct clk *pclk;
  struct clk *mclk;
  int irq;
  int n_pipelines;
  struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES];
  struct komeda_dev_funcs *funcs;
  void *chip_data;
  struct dentry *debugfs_root;


initialized by komeda_dev_funcs->init_format_table
APB clock for register access
irq number
chip funcs to access to HW
chip data will be added by komeda_dev_funcs.enum_resources() and destroyed by komeda_dev_funcs.cleanup()


Pipeline and component are used to describe how to handle the pixel data. komeda_device is for describing the whole view of the device, and the control-abilites of device.

Format handling

struct komeda_format_caps


struct komeda_format_caps {
  u32 hw_id;
  u32 fourcc;
  u32 tile_size;
  u32 supported_layer_types;
  u32 supported_rots;
  u32 supported_afbc_layouts;
  u64 supported_afbc_features;


hw format id, hw specific value.
drm fourcc format.
format tiled size, used by ARM format X0L0/X0L2
indicate which layer supports this format
allowed rotations for this format
supported afbc layerout
supported afbc features


komeda_format_caps is for describing ARM display specific features and limitations for a specific format, and format_caps will be linked into komeda_framebuffer like a extension of drm_format_info.


one fourcc may has two different format_caps items for fourcc and fourcc+modifier

struct komeda_format_caps_table

format_caps mananger


struct komeda_format_caps_table {
  u32 n_formats;
  const struct komeda_format_caps *format_caps;


the size of format_caps list.
format_caps list.

Attach komeda_dev to DRM-KMS

Komeda abstracts resources by pipeline/component, but DRM-KMS uses crtc/plane/connector. One KMS-obj cannot represent only one single component, since the requirements of a single KMS object cannot simply be achieved by a single component, usually that needs multiple components to fit the requirement. Like set mode, gamma, ctm for KMS all target on CRTC-obj, but komeda needs compiz, improc and timing_ctrlr to work together to fit these requirements. And a KMS-Plane may require multiple komeda resources: layer/scaler/compiz.

So, one KMS-Obj represents a sub-pipeline of komeda resources.

So, for komeda, we treat KMS crtc/plane/connector as users of pipeline and component, and at any one time a pipeline/component only can be used by one user. And pipeline/component will be treated as private object of DRM-KMS; the state will be managed by drm_atomic_state as well.

How to map plane to Layer(input) pipeline

Komeda has multiple Layer input pipelines, see: - Single pipeline data flow - Dual pipeline with Slave enabled

The easiest way is binding a plane to a fixed Layer pipeline, but consider the komeda capabilities:

  • Layer Split, See Layer(input) pipeline

    Layer_Split is quite complicated feature, which splits a big image into two parts and handles it by two layers and two scalers individually. But it imports an edge problem or effect in the middle of the image after the split. To avoid such a problem, it needs a complicated Split calculation and some special configurations to the layer and scaler. We’d better hide such HW related complexity to user mode.

  • Slave pipeline, See Dual pipeline with Slave enabled

    Since the compiz component doesn’t output alpha value, the slave pipeline only can be used for bottom layers composition. The komeda driver wants to hide this limitation to the user. The way to do this is to pick a suitable Layer according to plane_state->zpos.

So for komeda, the KMS-plane doesn’t represent a fixed komeda layer pipeline, but multiple Layers with same capabilities. Komeda will select one or more Layers to fit the requirement of one KMS-plane.

Make component/pipeline to be drm_private_obj

Add drm_private_obj to komeda_component, komeda_pipeline

struct komeda_component {
    struct drm_private_obj obj;

struct komeda_pipeline {
    struct drm_private_obj obj;

Tracking component_state/pipeline_state by drm_atomic_state

Add drm_private_state and user to komeda_component_state, komeda_pipeline_state

struct komeda_component_state {
    struct drm_private_state obj;
    void *binding_user;

struct komeda_pipeline_state {
    struct drm_private_state obj;
    struct drm_crtc *crtc;

komeda component validation

Komeda has multiple types of components, but the process of validation are similar, usually including the following steps:

int komeda_xxxx_validate(struct komeda_component_xxx xxx_comp,
            struct komeda_component_output *input_dflow,
            struct drm_plane/crtc/connector *user,
            struct drm_plane/crtc/connector_state, *user_state)
     setup 1: check if component is needed, like the scaler is optional depending
              on the user_state; if unneeded, just return, and the caller will
              put the data flow into next stage.
     Setup 2: check user_state with component features and capabilities to see
              if requirements can be met; if not, return fail.
     Setup 3: get component_state from drm_atomic_state, and try set to set
              user to component; fail if component has been assigned to another
              user already.
     Setup 3: configure the component_state, like set its input component,
              convert user_state to component specific state.
     Setup 4: adjust the input_dflow and prepare it for the next stage.

komeda_kms Abstraction

struct komeda_plane_state


struct komeda_plane_state {
  struct drm_plane_state base;




The plane_state can be split into two data flow (left/right) and handled by two layers komeda_plane.layer and komeda_plane.layer.right

struct komeda_wb_connector


struct komeda_wb_connector {
  struct drm_writeback_connector base;
  struct komeda_layer *wb_layer;


represents associated writeback pipeline of komeda
struct komeda_crtc


struct komeda_crtc {
  struct drm_crtc base;
  struct komeda_pipeline *master;
  struct komeda_pipeline *slave;


only master has display output


Doesn’t have its own display output, the handled data flow will merge into the master.

komde_kms Functions

Build komeda to be a Linux module driver

Now we have two level devices:

  • komeda_dev: describes the real display hardware.
  • komeda_kms_dev: attachs or connects komeda_dev to DRM-KMS.

All komeda operations are supplied or operated by komeda_dev or komeda_kms_dev, the module driver is only a simple wrapper to pass the Linux command (probe/remove/pm) into komeda_dev or komeda_kms_dev.