Gallium3D: gallium/drivers/i965simple/brw

#define ALU1 ( OP )

Value:

struct brw_instruction *brw_##OP(struct brw_compile *p, \
              struct brw_reg dest,                      \
              struct brw_reg src0);

Definition at line 710 of file brw_eu.h.

#define ALU2 ( OP )

Value:

struct brw_instruction *brw_##OP(struct brw_compile *p, \
              struct brw_reg dest,                      \
              struct brw_reg src0,                      \
              struct brw_reg src1);

Definition at line 715 of file brw_eu.h.

#define BRW_EU_MAX_INSN 1200

Definition at line 97 of file brw_eu.h.

#define BRW_EU_MAX_INSN_STACK 5

Definition at line 96 of file brw_eu.h.

#define BRW_GET_SWZ	(	swz,
		idx		)	(((swz) >> ((idx)*2)) & 0x3)

Definition at line 43 of file brw_eu.h.

#define BRW_SWIZZLE4	(	a,
		b,
		c,
		d	)	(((a)<<0) \| ((b)<<2) \| ((c)<<4) \| ((d)<<6))

Definition at line 42 of file brw_eu.h.

#define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)

Definition at line 45 of file brw_eu.h.

#define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)

Definition at line 47 of file brw_eu.h.

#define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)

Definition at line 48 of file brw_eu.h.

#define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)

Definition at line 46 of file brw_eu.h.

#define REG_SIZE (8*4)

Definition at line 51 of file brw_eu.h.

#define VF_NEG (1<<7)

Definition at line 380 of file brw_eu.h.

#define VF_ONE 0x30

Definition at line 379 of file brw_eu.h.

#define VF_ZERO 0x0

Definition at line 378 of file brw_eu.h.

static __inline struct brw_reg brw_abs ( struct brw_reg reg ) [static, read]

Definition at line 605 of file brw_eu.h.

References brw_reg::abs.

00606 {
00607    reg.abs = 1;
00608    return reg;
00609 }

static __inline struct brw_reg brw_acc_reg ( void ) [static, read]

Definition at line 467 of file brw_eu.h.

References BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ACCUMULATOR, and brw_vec8_reg().

00468 {
00469    return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
00470                        BRW_ARF_ACCUMULATOR,
00471                        0);
00472 }

struct brw_instruction* brw_ADD	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 423 of file brw_eu_emit.c.

00440 {

static __inline struct brw_reg brw_address ( struct brw_reg reg ) [static, read]

Definition at line 399 of file brw_eu.h.

References brw_imm_uw(), and REG_SIZE.

00400 {
00401    return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr);
00402 }

static __inline struct brw_reg brw_address_reg ( unsigned subnr ) [static, read]

Definition at line 443 of file brw_eu.h.

References BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ADDRESS, brw_uw1_reg(), and brw_reg::subnr.

00444 {
00445    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
00446                       BRW_ARF_ADDRESS,
00447                       subnr);
00448 }

struct brw_instruction* brw_alu1	(	struct brw_compile *	p,
		unsigned	opcode,
		struct brw_reg	dest,
		struct brw_reg	src
	)			`[read]`

Definition at line 366 of file brw_eu_emit.c.

References brw_set_dest(), brw_set_src0(), and next_insn().

00370 {
00371    struct brw_instruction *insn = next_insn(p, opcode);
00372    brw_set_dest(insn, dest);
00373    brw_set_src0(insn, src);
00374    return insn;
00375 }

struct brw_instruction* brw_alu2	(	struct brw_compile *	p,
		unsigned	opcode,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 377 of file brw_eu_emit.c.

References brw_set_dest(), brw_set_src0(), brw_set_src1(), and next_insn().

00382 {
00383    struct brw_instruction *insn = next_insn(p, opcode);
00384    brw_set_dest(insn, dest);
00385    brw_set_src0(insn, src0);
00386    brw_set_src1(insn, src1);
00387    return insn;
00388 }

struct brw_instruction* brw_AND	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 415 of file brw_eu_emit.c.

00440 {

struct brw_instruction* brw_ASR	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 422 of file brw_eu_emit.c.

00440 {

struct brw_instruction* brw_BREAK ( struct brw_compile * p ) [read]

Definition at line 600 of file brw_eu_emit.c.

References brw_instruction::bits3, BRW_COMPRESSION_NONE, BRW_EXECUTE_8, brw_imm_d(), brw_ip_reg(), BRW_MASK_DISABLE, BRW_OPCODE_BREAK, brw_set_dest(), brw_set_src0(), brw_set_src1(), brw_instruction::compression_control, brw_instruction::execution_size, brw_instruction::header, brw_instruction::if_else, brw_instruction::mask_control, and next_insn().

00601 {
00602    struct brw_instruction *insn;
00603    insn = next_insn(p, BRW_OPCODE_BREAK);
00604    brw_set_dest(insn, brw_ip_reg());
00605    brw_set_src0(insn, brw_ip_reg());
00606    brw_set_src1(insn, brw_imm_d(0x0));
00607    insn->header.compression_control = BRW_COMPRESSION_NONE;
00608    insn->header.execution_size = BRW_EXECUTE_8;
00609    insn->header.mask_control = BRW_MASK_DISABLE;
00610    insn->bits3.if_else.pad0 = 0;
00611    return insn;
00612 }

void brw_CMP	(	struct brw_compile *	p,
		struct brw_reg	dest,
		unsigned	conditional,
		struct brw_reg	src0,
		struct brw_reg	src1
	)

Definition at line 711 of file brw_eu_emit.c.

References BRW_ARCHITECTURE_REGISTER_FILE, BRW_OPCODE_CMP, BRW_PREDICATE_NORMAL, brw_set_dest(), brw_set_src0(), brw_set_src1(), brw_compile::current, brw_instruction::destreg__conditonalmod, brw_reg::file, brw_compile::flag_value, brw_instruction::header, next_insn(), brw_reg::nr, and brw_instruction::predicate_control.

00716 {
00717    struct brw_instruction *insn = next_insn(p, BRW_OPCODE_CMP);
00718 
00719    insn->header.destreg__conditonalmod = conditional;
00720    brw_set_dest(insn, dest);
00721    brw_set_src0(insn, src0);
00722    brw_set_src1(insn, src1);
00723 
00724 /*    guess_execution_size(insn, src0); */
00725 
00726 
00727    /* Make it so that future instructions will use the computed flag
00728     * value until brw_set_predicate_control_flag_value() is called
00729     * again.
00730     */
00731    if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
00732        dest.nr == 0) {
00733       p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
00734       p->flag_value = 0xff;
00735    }
00736 }

struct brw_instruction* brw_CONT ( struct brw_compile * p ) [read]

Definition at line 614 of file brw_eu_emit.c.

References brw_instruction::bits3, BRW_COMPRESSION_NONE, BRW_EXECUTE_8, brw_imm_d(), brw_ip_reg(), BRW_MASK_DISABLE, BRW_OPCODE_CONTINUE, brw_set_dest(), brw_set_src0(), brw_set_src1(), brw_instruction::compression_control, brw_instruction::execution_size, brw_instruction::header, brw_instruction::if_else, brw_instruction::mask_control, and next_insn().

00615 {
00616    struct brw_instruction *insn;
00617    insn = next_insn(p, BRW_OPCODE_CONTINUE);
00618    brw_set_dest(insn, brw_ip_reg());
00619    brw_set_src0(insn, brw_ip_reg());
00620    brw_set_src1(insn, brw_imm_d(0x0));
00621    insn->header.compression_control = BRW_COMPRESSION_NONE;
00622    insn->header.execution_size = BRW_EXECUTE_8;
00623    insn->header.mask_control = BRW_MASK_DISABLE;
00624    insn->bits3.if_else.pad0 = 0;
00625    return insn;
00626 }

void brw_copy4	(	struct brw_compile *	p,
		struct brw_reg	dst,
		struct brw_reg	src,
		unsigned	count
	)

Definition at line 54 of file brw_eu_util.c.

References brw_MOV(), byte_offset(), and vec4().

00058 {
00059    unsigned i;
00060 
00061    dst = vec4(dst);
00062    src = vec4(src);
00063 
00064    for (i = 0; i < count; i++)
00065    {
00066       unsigned delta = i*32;
00067       brw_MOV(p, byte_offset(dst, delta),    byte_offset(src, delta));
00068       brw_MOV(p, byte_offset(dst, delta+16), byte_offset(src, delta+16));
00069    }
00070 }

void brw_copy8	(	struct brw_compile *	p,
		struct brw_reg	dst,
		struct brw_reg	src,
		unsigned	count
	)

Definition at line 73 of file brw_eu_util.c.

References brw_MOV(), byte_offset(), and vec8().

00077 {
00078    unsigned i;
00079 
00080    dst = vec8(dst);
00081    src = vec8(src);
00082 
00083    for (i = 0; i < count; i++)
00084    {
00085       unsigned delta = i*32;
00086       brw_MOV(p, byte_offset(dst, delta),    byte_offset(src, delta));
00087    }
00088 }

void brw_copy_from_indirect	(	struct brw_compile *	p,
		struct brw_reg	dst,
		struct brw_indirect	ptr,
		unsigned	count
	)

Definition at line 107 of file brw_eu_util.c.

References brw_MOV(), byte_offset(), deref_4f(), and vec4().

00111 {
00112    unsigned i;
00113 
00114    dst = vec4(dst);
00115 
00116    for (i = 0; i < count; i++)
00117    {
00118       unsigned delta = i*32;
00119       brw_MOV(p, byte_offset(dst, delta),    deref_4f(ptr, delta));
00120       brw_MOV(p, byte_offset(dst, delta+16), deref_4f(ptr, delta+16));
00121    }
00122 }

void brw_copy_indirect_to_indirect	(	struct brw_compile *	p,
		struct brw_indirect	dst_ptr,
		struct brw_indirect	src_ptr,
		unsigned	count
	)

Definition at line 91 of file brw_eu_util.c.

References brw_MOV(), and deref_4f().

00095 {
00096    unsigned i;
00097 
00098    for (i = 0; i < count; i++)
00099    {
00100       unsigned delta = i*32;
00101       brw_MOV(p, deref_4f(dst_ptr, delta),    deref_4f(src_ptr, delta));
00102       brw_MOV(p, deref_4f(dst_ptr, delta+16), deref_4f(src_ptr, delta+16));
00103    }
00104 }

struct brw_instruction* brw_DO	(	struct brw_compile *	p,
		unsigned	execute_size
	)			`[read]`

Definition at line 630 of file brw_eu_emit.c.

References BRW_COMPRESSION_NONE, BRW_MASK_DISABLE, brw_null_reg(), BRW_OPCODE_DO, BRW_PREDICATE_NONE, brw_set_dest(), brw_set_src0(), brw_set_src1(), brw_instruction::compression_control, brw_instruction::execution_size, brw_instruction::header, brw_instruction::mask_control, next_insn(), brw_compile::nr_insn, brw_instruction::predicate_control, brw_compile::single_program_flow, and brw_compile::store.

00631 {
00632    if (p->single_program_flow) {
00633       return &p->store[p->nr_insn];
00634    } else {
00635       struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO);
00636 
00637       /* Override the defaults for this instruction:
00638        */
00639       brw_set_dest(insn, brw_null_reg());
00640       brw_set_src0(insn, brw_null_reg());
00641       brw_set_src1(insn, brw_null_reg());
00642 
00643       insn->header.compression_control = BRW_COMPRESSION_NONE;
00644       insn->header.execution_size = execute_size;
00645       insn->header.predicate_control = BRW_PREDICATE_NONE;
00646       /* insn->header.mask_control = BRW_MASK_ENABLE; */
00647       insn->header.mask_control = BRW_MASK_DISABLE;
00648 
00649       return insn;
00650    }
00651 }

struct brw_instruction* brw_DP2	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 433 of file brw_eu_emit.c.

00440 {

struct brw_instruction* brw_DP3	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 432 of file brw_eu_emit.c.

00440 {

struct brw_instruction* brw_DP4	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 430 of file brw_eu_emit.c.

00440 {

void brw_dp_READ_16	(	struct brw_compile *	p,
		struct brw_reg	dest,
		unsigned	msg_reg_nr,
		unsigned	scratch_offset
	)

Definition at line 873 of file brw_eu_emit.c.

References BRW_COMPRESSION_NONE, BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, brw_imm_d(), BRW_MASK_DISABLE, brw_MOV(), BRW_OPCODE_SEND, brw_pop_insn_state(), brw_push_insn_state(), BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_UW, brw_set_compression_control(), brw_set_dest(), brw_set_dp_read_message(), brw_set_mask_control(), brw_set_src0(), brw_vec1_grf(), brw_vec8_grf(), brw_instruction::compression_control, brw_instruction::destreg__conditonalmod, brw_instruction::header, next_insn(), brw_instruction::predicate_control, and retype().

00877 {
00878    {
00879       brw_push_insn_state(p);
00880       brw_set_compression_control(p, BRW_COMPRESSION_NONE);
00881       brw_set_mask_control(p, BRW_MASK_DISABLE);
00882 
00883       brw_MOV(p,
00884               retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_D),
00885               brw_imm_d(scratch_offset));
00886 
00887       brw_pop_insn_state(p);
00888    }
00889 
00890    {
00891       struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
00892 
00893       insn->header.predicate_control = 0; /* XXX */
00894       insn->header.compression_control = BRW_COMPRESSION_NONE;
00895       insn->header.destreg__conditonalmod = msg_reg_nr;
00896 
00897       brw_set_dest(insn, dest); /* UW? */
00898       brw_set_src0(insn, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW));
00899 
00900       brw_set_dp_read_message(insn,
00901                               255, /* bti */
00902                               3,  /* msg_control */
00903                               BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */
00904                               1, /* target cache */
00905                               1, /* msg_length */
00906                               2, /* response_length */
00907                               0); /* eot */
00908    }
00909 }

void brw_dp_WRITE_16	(	struct brw_compile *	p,
		struct brw_reg	src,
		unsigned	msg_reg_nr,
		unsigned	scratch_offset
	)

Definition at line 831 of file brw_eu_emit.c.

References BRW_COMPRESSION_NONE, BRW_DATAPORT_OWORD_BLOCK_4_OWORDS, BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE, brw_imm_d(), BRW_MASK_DISABLE, brw_MOV(), brw_null_reg(), BRW_OPCODE_SEND, brw_pop_insn_state(), brw_push_insn_state(), BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_UW, brw_set_compression_control(), brw_set_dest(), brw_set_dp_write_message(), brw_set_mask_control(), brw_set_src0(), brw_vec1_grf(), brw_instruction::compression_control, brw_instruction::destreg__conditonalmod, brw_instruction::header, brw_instruction::msg_length, next_insn(), brw_instruction::predicate_control, and retype().

00835 {
00836    {
00837       brw_push_insn_state(p);
00838       brw_set_mask_control(p, BRW_MASK_DISABLE);
00839       brw_set_compression_control(p, BRW_COMPRESSION_NONE);
00840 
00841       brw_MOV(p,
00842               retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_D),
00843               brw_imm_d(scratch_offset));
00844 
00845       brw_pop_insn_state(p);
00846    }
00847 
00848    {
00849       unsigned msg_length = 3;
00850       struct brw_reg dest = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW);
00851       struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
00852 
00853       insn->header.predicate_control = 0; /* XXX */
00854       insn->header.compression_control = BRW_COMPRESSION_NONE;
00855       insn->header.destreg__conditonalmod = msg_reg_nr;
00856 
00857       brw_set_dest(insn, dest);
00858       brw_set_src0(insn, src);
00859 
00860       brw_set_dp_write_message(insn,
00861                                255, /* bti */
00862                                BRW_DATAPORT_OWORD_BLOCK_4_OWORDS, /* msg_control */
00863                                BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE, /* msg_type */
00864                                msg_length,
00865                                0, /* pixel scoreboard */
00866                                0, /* response_length */
00867                                0); /* eot */
00868    }
00869 
00870 }

struct brw_instruction* brw_DPH	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 431 of file brw_eu_emit.c.

00440 {

struct brw_instruction* brw_ELSE	(	struct brw_compile *	p,
		struct brw_instruction *	if_insn
	)			`[read]`

Definition at line 512 of file brw_eu_emit.c.

References assert, brw_instruction::bits3, BRW_COMPRESSION_NONE, brw_imm_d(), brw_ip_reg(), BRW_MASK_ENABLE, BRW_OPCODE_ADD, BRW_OPCODE_ELSE, BRW_OPCODE_IF, brw_set_dest(), brw_set_src0(), brw_set_src1(), brw_instruction::compression_control, brw_instruction::execution_size, brw_instruction::header, brw_instruction::if_else, brw_instruction::mask_control, next_insn(), brw_instruction::opcode, brw_compile::single_program_flow, and brw_instruction::ud.

00514 {
00515    struct brw_instruction *insn;
00516 
00517    if (p->single_program_flow) {
00518       insn = next_insn(p, BRW_OPCODE_ADD);
00519    } else {
00520       insn = next_insn(p, BRW_OPCODE_ELSE);
00521    }
00522 
00523    brw_set_dest(insn, brw_ip_reg());
00524    brw_set_src0(insn, brw_ip_reg());
00525    brw_set_src1(insn, brw_imm_d(0x0));
00526 
00527    insn->header.compression_control = BRW_COMPRESSION_NONE;
00528    insn->header.execution_size = if_insn->header.execution_size;
00529    insn->header.mask_control = BRW_MASK_ENABLE;
00530 
00531    /* Patch the if instruction to point at this instruction.
00532     */
00533    if (p->single_program_flow) {
00534       assert(if_insn->header.opcode == BRW_OPCODE_ADD);
00535 
00536       if_insn->bits3.ud = (insn - if_insn + 1) * 16;
00537    } else {
00538       assert(if_insn->header.opcode == BRW_OPCODE_IF);
00539 
00540       if_insn->bits3.if_else.jump_count = insn - if_insn;
00541       if_insn->bits3.if_else.pop_count = 1;
00542       if_insn->bits3.if_else.pad0 = 0;
00543    }
00544 
00545    return insn;
00546 }

void brw_ENDIF	(	struct brw_compile *	p,
		struct brw_instruction *	if_or_else_insn
	)

Definition at line 548 of file brw_eu_emit.c.

References assert, brw_instruction::bits3, BRW_COMPRESSION_NONE, brw_imm_d(), BRW_MASK_ENABLE, BRW_OPCODE_ADD, BRW_OPCODE_ELSE, BRW_OPCODE_ENDIF, BRW_OPCODE_IF, BRW_OPCODE_IFF, BRW_REGISTER_TYPE_UD, brw_set_dest(), brw_set_src0(), brw_set_src1(), brw_vec4_grf(), brw_instruction::compression_control, brw_instruction::execution_size, brw_instruction::header, brw_instruction::if_else, brw_instruction::mask_control, next_insn(), brw_compile::nr_insn, brw_instruction::opcode, retype(), brw_compile::single_program_flow, brw_compile::store, and brw_instruction::ud.

00550 {
00551    if (p->single_program_flow) {
00552       /* In single program flow mode, there's no need to execute an ENDIF,
00553        * since we don't need to do any stack operations, and if we're executing
00554        * currently, we want to just continue executing.
00555        */
00556       struct brw_instruction *next = &p->store[p->nr_insn];
00557 
00558       assert(patch_insn->header.opcode == BRW_OPCODE_ADD);
00559 
00560       patch_insn->bits3.ud = (next - patch_insn) * 16;
00561    } else {
00562       struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ENDIF);
00563 
00564       brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
00565       brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
00566       brw_set_src1(insn, brw_imm_d(0x0));
00567 
00568       insn->header.compression_control = BRW_COMPRESSION_NONE;
00569       insn->header.execution_size = patch_insn->header.execution_size;
00570       insn->header.mask_control = BRW_MASK_ENABLE;
00571 
00572       assert(patch_insn->bits3.if_else.jump_count == 0);
00573 
00574       /* Patch the if or else instructions to point at this or the next
00575        * instruction respectively.
00576        */
00577       if (patch_insn->header.opcode == BRW_OPCODE_IF) {
00578          /* Automagically turn it into an IFF:
00579           */
00580          patch_insn->header.opcode = BRW_OPCODE_IFF;
00581          patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1;
00582          patch_insn->bits3.if_else.pop_count = 0;
00583          patch_insn->bits3.if_else.pad0 = 0;
00584       } else if (patch_insn->header.opcode == BRW_OPCODE_ELSE) {
00585          patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1;
00586          patch_insn->bits3.if_else.pop_count = 1;
00587          patch_insn->bits3.if_else.pad0 = 0;
00588       } else {
00589          assert(0);
00590       }
00591 
00592       /* Also pop item off the stack in the endif instruction:
00593        */
00594       insn->bits3.if_else.jump_count = 0;
00595       insn->bits3.if_else.pop_count = 1;
00596       insn->bits3.if_else.pad0 = 0;
00597    }
00598 }

void brw_fb_WRITE	(	struct brw_compile *	p,
		struct brw_reg	dest,
		unsigned	msg_reg_nr,
		struct brw_reg	src0,
		unsigned	binding_table_index,
		unsigned	msg_length,
		unsigned	response_length,
		boolean	eot
	)

Definition at line 912 of file brw_eu_emit.c.

References BRW_COMPRESSION_NONE, BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE, BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE, BRW_OPCODE_SEND, brw_set_dest(), brw_set_dp_write_message(), brw_set_src0(), brw_instruction::compression_control, brw_instruction::destreg__conditonalmod, brw_instruction::header, next_insn(), and brw_instruction::predicate_control.

00920 {
00921    struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
00922 
00923    insn->header.predicate_control = 0; /* XXX */
00924    insn->header.compression_control = BRW_COMPRESSION_NONE;
00925    insn->header.destreg__conditonalmod = msg_reg_nr;
00926 
00927    brw_set_dest(insn, dest);
00928    brw_set_src0(insn, src0);
00929    brw_set_dp_write_message(insn,
00930                             binding_table_index,
00931                             BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE, /* msg_control */
00932                             BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE, /* msg_type */
00933                             msg_length,
00934                             1,  /* pixel scoreboard */
00935                             response_length,
00936                             eot);
00937 }

static __inline struct brw_reg brw_flag_reg ( void ) [static, read]

Definition at line 475 of file brw_eu.h.

References BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_FLAG, and brw_uw1_reg().

00476 {
00477    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
00478                       BRW_ARF_FLAG,
00479                       0);
00480 }

struct brw_instruction* brw_FRC	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0
	)			`[read]`

Definition at line 425 of file brw_eu_emit.c.

00440 {

const unsigned* brw_get_program	(	struct brw_compile *	p,
		unsigned *	sz
	)

Definition at line 119 of file brw_eu.c.

References brw_NOP(), brw_compile::nr_insn, and brw_compile::store.

00121 {
00122    unsigned i;
00123 
00124    for (i = 0; i < 8; i++)
00125       brw_NOP(p);
00126 
00127    *sz = p->nr_insn * sizeof(struct brw_instruction);
00128    return (const unsigned *)p->store;
00129 }

struct brw_instruction* brw_IF	(	struct brw_compile *	p,
		unsigned	execute_size
	)			`[read]`

Definition at line 482 of file brw_eu_emit.c.

References assert, BRW_COMPRESSION_NONE, BRW_EXECUTE_1, brw_imm_d(), brw_ip_reg(), BRW_MASK_ENABLE, BRW_OPCODE_ADD, BRW_OPCODE_IF, BRW_PREDICATE_NONE, BRW_PREDICATE_NORMAL, brw_set_dest(), brw_set_src0(), brw_set_src1(), brw_instruction::compression_control, brw_compile::current, brw_instruction::execution_size, brw_instruction::header, brw_instruction::mask_control, next_insn(), brw_instruction::predicate_control, brw_instruction::predicate_inverse, and brw_compile::single_program_flow.

00483 {
00484    struct brw_instruction *insn;
00485 
00486    if (p->single_program_flow) {
00487       assert(execute_size == BRW_EXECUTE_1);
00488 
00489       insn = next_insn(p, BRW_OPCODE_ADD);
00490       insn->header.predicate_inverse = 1;
00491    } else {
00492       insn = next_insn(p, BRW_OPCODE_IF);
00493    }
00494 
00495    /* Override the defaults for this instruction:
00496     */
00497    brw_set_dest(insn, brw_ip_reg());
00498    brw_set_src0(insn, brw_ip_reg());
00499    brw_set_src1(insn, brw_imm_d(0x0));
00500 
00501    insn->header.execution_size = execute_size;
00502    insn->header.compression_control = BRW_COMPRESSION_NONE;
00503    insn->header.predicate_control = BRW_PREDICATE_NORMAL;
00504    insn->header.mask_control = BRW_MASK_ENABLE;
00505 
00506    p->current->header.predicate_control = BRW_PREDICATE_NONE;
00507 
00508    return insn;
00509 }

static __inline struct brw_reg brw_imm_d ( int d ) [static, read]

Definition at line 322 of file brw_eu.h.

References brw_imm_reg(), BRW_REGISTER_TYPE_D, brw_reg::d, and brw_reg::dw1.

00323 {
00324    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
00325    imm.dw1.d = d;
00326    return imm;
00327 }

static __inline struct brw_reg brw_imm_f ( float f ) [static, read]

Definition at line 315 of file brw_eu.h.

References brw_imm_reg(), BRW_REGISTER_TYPE_F, brw_reg::dw1, and brw_reg::f.

00316 {
00317    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
00318    imm.dw1.f = f;
00319    return imm;
00320 }

static __inline struct brw_reg brw_imm_reg ( unsigned type ) [static, read]

Definition at line 302 of file brw_eu.h.

References BRW_HORIZONTAL_STRIDE_0, BRW_IMMEDIATE_VALUE, brw_reg(), BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, and brw_reg::type.

00303 {
00304    return brw_reg( BRW_IMMEDIATE_VALUE,
00305                    0,
00306                    0,
00307                    type,
00308                    BRW_VERTICAL_STRIDE_0,
00309                    BRW_WIDTH_1,
00310                    BRW_HORIZONTAL_STRIDE_0,
00311                    0,
00312                    0);
00313 }

static __inline struct brw_reg brw_imm_ud ( unsigned ud ) [static, read]

Definition at line 329 of file brw_eu.h.

References brw_imm_reg(), BRW_REGISTER_TYPE_UD, brw_reg::dw1, and brw_reg::ud.

00330 {
00331    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
00332    imm.dw1.ud = ud;
00333    return imm;
00334 }

static __inline struct brw_reg brw_imm_uw ( ushort uw ) [static, read]

Definition at line 336 of file brw_eu.h.

References brw_imm_reg(), BRW_REGISTER_TYPE_UW, brw_reg::dw1, and brw_reg::ud.

00337 {
00338    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
00339    imm.dw1.ud = uw;
00340    return imm;
00341 }

static __inline struct brw_reg brw_imm_v ( unsigned v ) [static, read]

Definition at line 356 of file brw_eu.h.

References BRW_HORIZONTAL_STRIDE_1, brw_imm_reg(), BRW_REGISTER_TYPE_V, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_8, brw_reg::dw1, brw_reg::hstride, brw_reg::ud, brw_reg::vstride, and brw_reg::width.

00357 {
00358    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);
00359    imm.vstride = BRW_VERTICAL_STRIDE_0;
00360    imm.width = BRW_WIDTH_8;
00361    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
00362    imm.dw1.ud = v;
00363    return imm;
00364 }

static __inline struct brw_reg brw_imm_vf ( unsigned v ) [static, read]

Definition at line 368 of file brw_eu.h.

References BRW_HORIZONTAL_STRIDE_1, brw_imm_reg(), BRW_REGISTER_TYPE_VF, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_4, brw_reg::dw1, brw_reg::hstride, brw_reg::ud, brw_reg::vstride, and brw_reg::width.

00369 {
00370    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
00371    imm.vstride = BRW_VERTICAL_STRIDE_0;
00372    imm.width = BRW_WIDTH_4;
00373    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
00374    imm.dw1.ud = v;
00375    return imm;
00376 }

static __inline struct brw_reg brw_imm_vf4	(	unsigned	v0,
		unsigned	v1,
		unsigned	v2,
		unsigned	v3
	)			`[static, read]`

Definition at line 382 of file brw_eu.h.

References BRW_HORIZONTAL_STRIDE_1, brw_imm_reg(), BRW_REGISTER_TYPE_VF, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_4, brw_reg::dw1, brw_reg::hstride, brw_reg::ud, brw_reg::vstride, and brw_reg::width.

00386 {
00387    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
00388    imm.vstride = BRW_VERTICAL_STRIDE_0;
00389    imm.width = BRW_WIDTH_4;
00390    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
00391    imm.dw1.ud = ((v0 << 0) |
00392                  (v1 << 8) |
00393                  (v2 << 16) |
00394                  (v3 << 24));
00395    return imm;
00396 }

static __inline struct brw_reg brw_imm_w ( short w ) [static, read]

Definition at line 343 of file brw_eu.h.

References brw_imm_reg(), BRW_REGISTER_TYPE_W, brw_reg::d, and brw_reg::dw1.

00344 {
00345    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
00346    imm.dw1.d = w;
00347    return imm;
00348 }

static __inline struct brw_indirect brw_indirect	(	unsigned	addr_subnr,
		int	offset
	)			`[static, read]`

Definition at line 669 of file brw_eu.h.

References brw_indirect::addr_offset, brw_indirect::addr_subnr, offset(), and brw_indirect::pad.

00670 {
00671    struct brw_indirect ptr;
00672    ptr.addr_subnr = addr_subnr;
00673    ptr.addr_offset = offset;
00674    ptr.pad = 0;
00675    return ptr;
00676 }

static __inline struct brw_indirect brw_indirect_offset	(	struct brw_indirect	ptr,
		int	offset
	)			`[static, read]`

Definition at line 663 of file brw_eu.h.

References brw_indirect::addr_offset, and offset().

00664 {
00665    ptr.addr_offset += offset;
00666    return ptr;
00667 }

void brw_init_compile ( struct brw_compile * p )

Definition at line 104 of file brw_eu.c.

References BRW_COMPRESSION_NONE, BRW_MASK_ENABLE, brw_set_compression_control(), brw_set_mask_control(), brw_set_predicate_control_flag_value(), brw_set_saturate(), brw_compile::current, brw_compile::nr_insn, and brw_compile::stack.

00105 {
00106    p->nr_insn = 0;
00107    p->current = p->stack;
00108    memset(p->current, 0, sizeof(p->current[0]));
00109 
00110    /* Some defaults?
00111     */
00112    brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
00113    brw_set_saturate(p, 0);
00114    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
00115    brw_set_predicate_control_flag_value(p, 0xff); 
00116 }

static __inline struct brw_reg brw_ip_reg ( void ) [static, read]

Definition at line 454 of file brw_eu.h.

References BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_IP, BRW_HORIZONTAL_STRIDE_0, brw_reg(), BRW_REGISTER_TYPE_UD, BRW_SWIZZLE_XYZW, BRW_VERTICAL_STRIDE_4, BRW_WIDTH_1, and TGSI_WRITEMASK_XYZW.

00455 {
00456    return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
00457                   BRW_ARF_IP,
00458                   0,
00459                   BRW_REGISTER_TYPE_UD,
00460                   BRW_VERTICAL_STRIDE_4, /* ? */
00461                   BRW_WIDTH_1,
00462                   BRW_HORIZONTAL_STRIDE_0,
00463                   BRW_SWIZZLE_XYZW, /* NOTE! */
00464                   TGSI_WRITEMASK_XYZW); /* NOTE! */
00465 }

struct brw_instruction* brw_JMPI	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 455 of file brw_eu_emit.c.

References brw_alu2(), BRW_OPCODE_JMPI, BRW_PREDICATE_NONE, brw_compile::current, brw_instruction::header, and brw_instruction::predicate_control.

00459 {
00460    struct brw_instruction *insn = brw_alu2(p, BRW_OPCODE_JMPI, dest, src0, src1);
00461 
00462    p->current->header.predicate_control = BRW_PREDICATE_NONE;
00463 
00464    return insn;
00465 }

void brw_land_fwd_jump	(	struct brw_compile *	p,
		struct brw_instruction *	jmp_insn
	)

Definition at line 694 of file brw_eu_emit.c.

References assert, brw_instruction::bits1, brw_instruction::bits3, BRW_IMMEDIATE_VALUE, BRW_OPCODE_JMPI, brw_instruction::da1, brw_instruction::header, brw_compile::nr_insn, brw_instruction::opcode, brw_compile::store, and brw_instruction::ud.

00696 {
00697    struct brw_instruction *landing = &p->store[p->nr_insn];
00698 
00699    assert(jmp_insn->header.opcode == BRW_OPCODE_JMPI);
00700    assert(jmp_insn->bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE);
00701 
00702    jmp_insn->bits3.ud = (landing - jmp_insn) - 1;
00703 }

struct brw_instruction* brw_LINE	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 434 of file brw_eu_emit.c.

00440 {

struct brw_instruction* brw_LZD	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0
	)			`[read]`

Definition at line 429 of file brw_eu_emit.c.

00440 {

struct brw_instruction* brw_MAC	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 427 of file brw_eu_emit.c.

00440 {

struct brw_instruction* brw_MACH	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 428 of file brw_eu_emit.c.

00440 {

static __inline struct brw_reg brw_mask_reg ( unsigned subnr ) [static, read]

Definition at line 483 of file brw_eu.h.

References BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_MASK, brw_uw1_reg(), and brw_reg::subnr.

00484 {
00485    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
00486                       BRW_ARF_MASK,
00487                       subnr);
00488 }

void brw_math	(	struct brw_compile *	p,
		struct brw_reg	dest,
		unsigned	function,
		unsigned	saturate,
		unsigned	msg_reg_nr,
		struct brw_reg	src,
		unsigned	data_type,
		unsigned	precision
	)

Definition at line 746 of file brw_eu_emit.c.

References BRW_MATH_FUNCTION_POW, BRW_MATH_FUNCTION_SINCOS, BRW_MATH_INTEGER_UNSIGNED, BRW_OPCODE_SEND, brw_set_dest(), brw_set_math_message(), brw_set_src0(), brw_instruction::destreg__conditonalmod, brw_instruction::header, brw_instruction::msg_length, next_insn(), brw_instruction::predicate_control, and brw_instruction::response_length.

00754 {
00755    struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
00756    unsigned msg_length = (function == BRW_MATH_FUNCTION_POW) ? 2 : 1;
00757    unsigned response_length = (function == BRW_MATH_FUNCTION_SINCOS) ? 2 : 1;
00758 
00759    /* Example code doesn't set predicate_control for send
00760     * instructions.
00761     */
00762    insn->header.predicate_control = 0;
00763    insn->header.destreg__conditonalmod = msg_reg_nr;
00764 
00765    brw_set_dest(insn, dest);
00766    brw_set_src0(insn, src);
00767    brw_set_math_message(insn,
00768                         msg_length, response_length,
00769                         function,
00770                         BRW_MATH_INTEGER_UNSIGNED,
00771                         precision,
00772                         saturate,
00773                         data_type);
00774 }

void brw_math_16	(	struct brw_compile *	p,
		struct brw_reg	dest,
		unsigned	function,
		unsigned	saturate,
		unsigned	msg_reg_nr,
		struct brw_reg	src,
		unsigned	precision
	)

Definition at line 778 of file brw_eu_emit.c.

References BRW_COMPRESSION_2NDHALF, BRW_COMPRESSION_NONE, BRW_MATH_DATA_VECTOR, BRW_MATH_FUNCTION_POW, BRW_MATH_FUNCTION_SINCOS, BRW_MATH_INTEGER_UNSIGNED, BRW_OPCODE_SEND, brw_pop_insn_state(), brw_push_insn_state(), brw_set_compression_control(), brw_set_dest(), brw_set_math_message(), brw_set_predicate_control_flag_value(), brw_set_src0(), brw_instruction::compression_control, brw_instruction::destreg__conditonalmod, brw_instruction::header, brw_instruction::msg_length, next_insn(), offset(), and brw_instruction::response_length.

00785 {
00786    struct brw_instruction *insn;
00787    unsigned msg_length = (function == BRW_MATH_FUNCTION_POW) ? 2 : 1;
00788    unsigned response_length = (function == BRW_MATH_FUNCTION_SINCOS) ? 2 : 1;
00789 
00790    /* First instruction:
00791     */
00792    brw_push_insn_state(p);
00793    brw_set_predicate_control_flag_value(p, 0xff);
00794    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
00795 
00796    insn = next_insn(p, BRW_OPCODE_SEND);
00797    insn->header.destreg__conditonalmod = msg_reg_nr;
00798 
00799    brw_set_dest(insn, dest);
00800    brw_set_src0(insn, src);
00801    brw_set_math_message(insn,
00802                         msg_length, response_length,
00803                         function,
00804                         BRW_MATH_INTEGER_UNSIGNED,
00805                         precision,
00806                         saturate,
00807                         BRW_MATH_DATA_VECTOR);
00808 
00809    /* Second instruction:
00810     */
00811    insn = next_insn(p, BRW_OPCODE_SEND);
00812    insn->header.compression_control = BRW_COMPRESSION_2NDHALF;
00813    insn->header.destreg__conditonalmod = msg_reg_nr+1;
00814 
00815    brw_set_dest(insn, offset(dest,1));
00816    brw_set_src0(insn, src);
00817    brw_set_math_message(insn,
00818                         msg_length, response_length,
00819                         function,
00820                         BRW_MATH_INTEGER_UNSIGNED,
00821                         precision,
00822                         saturate,
00823                         BRW_MATH_DATA_VECTOR);
00824 
00825    brw_pop_insn_state(p);
00826 }

void brw_math_invert	(	struct brw_compile *	p,
		struct brw_reg	dst,
		struct brw_reg	src
	)

Definition at line 38 of file brw_eu_util.c.

References brw_math(), BRW_MATH_DATA_VECTOR, BRW_MATH_FUNCTION_INV, BRW_MATH_PRECISION_FULL, and BRW_MATH_SATURATE_NONE.

00041 {
00042    brw_math( p, 
00043              dst,
00044              BRW_MATH_FUNCTION_INV, 
00045              BRW_MATH_SATURATE_NONE,
00046              0,
00047              src,
00048              BRW_MATH_PRECISION_FULL, 
00049              BRW_MATH_DATA_VECTOR );
00050 }

static __inline struct brw_reg brw_message_reg ( unsigned nr ) [static, read]

Definition at line 490 of file brw_eu.h.

References BRW_MESSAGE_REGISTER_FILE, brw_vec8_reg(), and brw_reg::nr.

00491 {
00492    return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE,
00493                        nr,
00494                        0);
00495 }

struct brw_instruction* brw_MOV	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0
	)			`[read]`

Definition at line 412 of file brw_eu_emit.c.

00440 {

struct brw_instruction* brw_MUL	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 424 of file brw_eu_emit.c.

00440 {

void brw_NOP ( struct brw_compile * p )

Definition at line 439 of file brw_eu_emit.c.

References brw_imm_ud(), BRW_OPCODE_NOP, BRW_REGISTER_TYPE_UD, brw_set_dest(), brw_set_src0(), brw_set_src1(), brw_vec4_grf(), next_insn(), and retype().

00440 {
00441    struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP);
00442    brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
00443    brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
00444    brw_set_src1(insn, brw_imm_ud(0x0));
00445 }

struct brw_instruction* brw_NOT	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0
	)			`[read]`

Definition at line 414 of file brw_eu_emit.c.

00440 {

static __inline struct brw_reg brw_null_reg ( void ) [static, read]

Definition at line 436 of file brw_eu.h.

References BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_NULL, and brw_vec8_reg().

00437 {
00438    return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
00439                        BRW_ARF_NULL,
00440                        0);
00441 }

struct brw_instruction* brw_OR	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 416 of file brw_eu_emit.c.

00440 {

void brw_pop_insn_state ( struct brw_compile * p )

Definition at line 95 of file brw_eu.c.

References assert, brw_compile::current, and brw_compile::stack.

00096 {
00097    assert(p->current != p->stack);
00098    p->current--;
00099 }

void brw_print_reg ( struct brw_reg reg )

Definition at line 37 of file brw_eu_debug.c.

References brw_reg::abs, BRW_GENERAL_REGISTER_FILE, BRW_HORIZONTAL_STRIDE_0, BRW_HORIZONTAL_STRIDE_1, BRW_REGISTER_TYPE_F, BRW_VERTICAL_STRIDE_0, BRW_VERTICAL_STRIDE_8, BRW_WIDTH_1, BRW_WIDTH_8, debug_printf(), brw_reg::file, brw_reg::hstride, brw_reg::negate, brw_reg::nr, brw_reg::subnr, brw_reg::type, type_sz(), brw_reg::vstride, and brw_reg::width.

00038 {
00039    static const char *file[] = {
00040       "arf",
00041       "grf",
00042       "msg",
00043       "imm"
00044    };
00045 
00046    static const char *type[] = {
00047       "ud",
00048       "d",
00049       "uw",
00050       "w",
00051       "ub",
00052       "vf",
00053       "hf",
00054       "f"
00055    };
00056 
00057    debug_printf("%s%s", 
00058                 hwreg.abs ? "abs/" : "",
00059                 hwreg.negate ? "-" : "");
00060      
00061    if (hwreg.file == BRW_GENERAL_REGISTER_FILE &&
00062        hwreg.nr % 2 == 0 &&
00063        hwreg.subnr == 0 &&
00064        hwreg.vstride == BRW_VERTICAL_STRIDE_8 &&
00065        hwreg.width == BRW_WIDTH_8 &&
00066        hwreg.hstride == BRW_HORIZONTAL_STRIDE_1 &&
00067        hwreg.type == BRW_REGISTER_TYPE_F) {
00068       debug_printf("vec%d", hwreg.nr);
00069    }
00070    else if (hwreg.file == BRW_GENERAL_REGISTER_FILE &&
00071             hwreg.vstride == BRW_VERTICAL_STRIDE_0 &&
00072             hwreg.width == BRW_WIDTH_1 &&
00073             hwreg.hstride == BRW_HORIZONTAL_STRIDE_0 &&
00074             hwreg.type == BRW_REGISTER_TYPE_F) {      
00075       debug_printf("scl%d.%d", hwreg.nr, hwreg.subnr / 4);
00076    }
00077    else {
00078       debug_printf("%s%d.%d<%d;%d,%d>:%s", 
00079                    file[hwreg.file],
00080                    hwreg.nr,
00081                    hwreg.subnr / type_sz(hwreg.type),
00082                    hwreg.vstride ? (1<<(hwreg.vstride-1)) : 0,
00083                    1<<hwreg.width,
00084                    hwreg.hstride ? (1<<(hwreg.hstride-1)) : 0,          
00085                    type[hwreg.type]);
00086    }
00087 }

void brw_push_insn_state ( struct brw_compile * p )

Definition at line 88 of file brw_eu.c.

References assert, BRW_EU_MAX_INSN_STACK, brw_compile::current, and brw_compile::stack.

00089 {
00090    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
00091    memcpy(p->current+1, p->current, sizeof(struct brw_instruction));
00092    p->current++;   
00093 }

static __inline struct brw_reg brw_reg	(	unsigned	file,
		unsigned	nr,
		unsigned	subnr,
		unsigned	type,
		unsigned	vstride,
		unsigned	width,
		unsigned	hstride,
		unsigned	swizzle,
		unsigned	writemask
	)			`[static, read]`

Definition at line 133 of file brw_eu.h.

References brw_reg::abs, brw_reg::address_mode, brw_reg::bits, BRW_ADDRESS_DIRECT, brw_reg::dw1, brw_reg::file, brw_reg::hstride, brw_reg::negate, brw_reg::nr, brw_reg::pad0, brw_reg::subnr, brw_reg::swizzle, brw_reg::type, type_sz(), brw_reg::vstride, brw_reg::width, and brw_reg::writemask.

00142 {
00143 
00144    struct brw_reg reg;
00145    reg.type = type;
00146    reg.file = file;
00147    reg.nr = nr;
00148    reg.subnr = subnr * type_sz(type);
00149    reg.negate = 0;
00150    reg.abs = 0;
00151    reg.vstride = vstride;
00152    reg.width = width;
00153    reg.hstride = hstride;
00154    reg.address_mode = BRW_ADDRESS_DIRECT;
00155    reg.pad0 = 0;
00156 
00157    /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
00158     * set swizzle and writemask to W, as the lower bits of subnr will
00159     * be lost when converted to align16.  This is probably too much to
00160     * keep track of as you'd want it adjusted by suboffset(), etc.
00161     * Perhaps fix up when converting to align16?
00162     */
00163    reg.dw1.bits.swizzle = swizzle;
00164    reg.dw1.bits.writemask = writemask;
00165    reg.dw1.bits.indirect_offset = 0;
00166    reg.dw1.bits.pad1 = 0;
00167    return reg;
00168 }

struct brw_instruction* brw_RNDD	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0
	)			`[read]`

Definition at line 426 of file brw_eu_emit.c.

00440 {

struct brw_instruction* brw_RSL	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 421 of file brw_eu_emit.c.

00440 {

struct brw_instruction* brw_RSR	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 420 of file brw_eu_emit.c.

00440 {

void brw_SAMPLE	(	struct brw_compile *	p,
		struct brw_reg	dest,
		unsigned	msg_reg_nr,
		struct brw_reg	src0,
		unsigned	binding_table_index,
		unsigned	sampler,
		unsigned	writemask,
		unsigned	msg_type,
		unsigned	response_length,
		unsigned	msg_length,
		boolean	eot
	)

Definition at line 941 of file brw_eu_emit.c.

References BRW_COMPRESSION_NONE, brw_imm_ud(), BRW_MASK_DISABLE, brw_message_reg(), brw_MOV(), brw_null_reg(), BRW_OPCODE_SEND, brw_pop_insn_state(), brw_push_insn_state(), BRW_REGISTER_TYPE_UW, brw_set_compression_control(), brw_set_dest(), brw_set_mask_control(), brw_set_sampler_message(), brw_set_src0(), brw_vec8_grf(), brw_instruction::compression_control, brw_instruction::destreg__conditonalmod, FALSE, get_element_ud(), brw_instruction::header, next_insn(), offset(), brw_instruction::predicate_control, retype(), TGSI_WRITEMASK_XYZW, and vec8().

00952 {
00953    boolean need_stall = 0;
00954 
00955    if(writemask == 0) {
00956 /*       debug_printf("%s: zero writemask??\n", __FUNCTION__); */
00957       return;
00958    }
00959 
00960    /* Hardware doesn't do destination dependency checking on send
00961     * instructions properly.  Add a workaround which generates the
00962     * dependency by other means.  In practice it seems like this bug
00963     * only crops up for texture samples, and only where registers are
00964     * written by the send and then written again later without being
00965     * read in between.  Luckily for us, we already track that
00966     * information and use it to modify the writemask for the
00967     * instruction, so that is a guide for whether a workaround is
00968     * needed.
00969     */
00970    if (writemask != TGSI_WRITEMASK_XYZW) {
00971       unsigned dst_offset = 0;
00972       unsigned i, newmask = 0, len = 0;
00973 
00974       for (i = 0; i < 4; i++) {
00975          if (writemask & (1<<i))
00976             break;
00977          dst_offset += 2;
00978       }
00979       for (; i < 4; i++) {
00980          if (!(writemask & (1<<i)))
00981             break;
00982          newmask |= 1<<i;
00983          len++;
00984       }
00985 
00986       if (newmask != writemask) {
00987          need_stall = 1;
00988 /*       debug_printf("need stall %x %x\n", newmask , writemask); */
00989       }
00990       else {
00991          struct brw_reg m1 = brw_message_reg(msg_reg_nr);
00992 
00993          newmask = ~newmask & TGSI_WRITEMASK_XYZW;
00994 
00995          brw_push_insn_state(p);
00996 
00997          brw_set_compression_control(p, BRW_COMPRESSION_NONE);
00998          brw_set_mask_control(p, BRW_MASK_DISABLE);
00999 
01000          brw_MOV(p, m1, brw_vec8_grf(0,0));
01001          brw_MOV(p, get_element_ud(m1, 2), brw_imm_ud(newmask << 12));
01002 
01003          brw_pop_insn_state(p);
01004 
01005          src0 = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW);
01006          dest = offset(dest, dst_offset);
01007          response_length = len * 2;
01008       }
01009    }
01010 
01011    {
01012       struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
01013 
01014       insn->header.predicate_control = 0; /* XXX */
01015       insn->header.compression_control = BRW_COMPRESSION_NONE;
01016       insn->header.destreg__conditonalmod = msg_reg_nr;
01017 
01018       brw_set_dest(insn, dest);
01019       brw_set_src0(insn, src0);
01020       brw_set_sampler_message(insn,
01021                               binding_table_index,
01022                               sampler,
01023                               msg_type,
01024                               response_length,
01025                               msg_length,
01026                               eot);
01027    }
01028 
01029    if (need_stall)
01030    {
01031       struct brw_reg reg = vec8(offset(dest, response_length-1));
01032 
01033       /*  mov (8) r9.0<1>:f    r9.0<8;8,1>:f    { Align1 }
01034        */
01035       brw_push_insn_state(p);
01036       brw_set_compression_control(p, FALSE);
01037       brw_MOV(p, reg, reg);
01038       brw_pop_insn_state(p);
01039    }
01040 
01041 }

struct brw_instruction* brw_SEL	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 413 of file brw_eu_emit.c.

00440 {

void brw_set_access_mode	(	struct brw_compile *	p,
		unsigned	access_mode
	)

Definition at line 68 of file brw_eu.c.

References brw_instruction::access_mode, brw_compile::current, and brw_instruction::header.

00069 {
00070    p->current->header.access_mode = access_mode;
00071 }

void brw_set_compression_control	(	struct brw_compile *	p,
		boolean	control
	)

Definition at line 73 of file brw_eu.c.

References brw_instruction::compression_control, brw_compile::current, and brw_instruction::header.

00074 {
00075    p->current->header.compression_control = compression_control;
00076 }

void brw_set_conditionalmod	(	struct brw_compile *	p,
		unsigned	conditional
	)

Definition at line 63 of file brw_eu.c.

References brw_compile::current, brw_instruction::destreg__conditonalmod, and brw_instruction::header.

00064 {
00065    p->current->header.destreg__conditonalmod = conditional;
00066 }

void brw_set_mask_control	(	struct brw_compile *	p,
		unsigned	value
	)

Definition at line 78 of file brw_eu.c.

References brw_compile::current, brw_instruction::header, and brw_instruction::mask_control.

00079 {
00080    p->current->header.mask_control = value;
00081 }

void brw_set_predicate_control	(	struct brw_compile *	p,
		unsigned	pc
	)

Definition at line 58 of file brw_eu.c.

References brw_compile::current, brw_instruction::header, and brw_instruction::predicate_control.

00059 {
00060    p->current->header.predicate_control = pc;
00061 }

void brw_set_predicate_control_flag_value	(	struct brw_compile *	p,
		unsigned	value
	)

Definition at line 42 of file brw_eu.c.

References brw_flag_reg(), brw_imm_uw(), brw_MOV(), brw_pop_insn_state(), BRW_PREDICATE_NONE, BRW_PREDICATE_NORMAL, brw_push_insn_state(), brw_compile::current, brw_compile::flag_value, brw_instruction::header, and brw_instruction::predicate_control.

00043 {
00044    p->current->header.predicate_control = BRW_PREDICATE_NONE;
00045 
00046    if (value != 0xff) {
00047       if (value != p->flag_value) {
00048          brw_push_insn_state(p);
00049          brw_MOV(p, brw_flag_reg(), brw_imm_uw(value));
00050          p->flag_value = value;
00051          brw_pop_insn_state(p);
00052       }
00053 
00054       p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
00055    }   
00056 }

void brw_set_saturate	(	struct brw_compile *	p,
		unsigned	value
	)

Definition at line 83 of file brw_eu.c.

References brw_compile::current, brw_instruction::header, and brw_instruction::saturate.

00084 {
00085    p->current->header.saturate = value;
00086 }

void brw_set_src1	(	struct brw_instruction *	insn,
		struct brw_reg	reg
	)

Definition at line 167 of file brw_eu_emit.c.

References brw_reg::abs, brw_instruction::access_mode, brw_reg::address_mode, assert, brw_reg::bits, brw_instruction::bits1, brw_instruction::bits3, BRW_ADDRESS_DIRECT, BRW_ALIGN_1, BRW_CHANNEL_W, BRW_CHANNEL_X, BRW_CHANNEL_Y, BRW_CHANNEL_Z, BRW_EXECUTE_1, BRW_GET_SWZ, BRW_HORIZONTAL_STRIDE_0, BRW_IMMEDIATE_VALUE, BRW_MESSAGE_REGISTER_FILE, BRW_VERTICAL_STRIDE_0, BRW_VERTICAL_STRIDE_4, BRW_VERTICAL_STRIDE_8, BRW_WIDTH_1, brw_instruction::da1, brw_instruction::da16, brw_reg::dw1, brw_instruction::execution_size, brw_reg::file, brw_instruction::header, brw_reg::hstride, brw_reg::negate, brw_reg::nr, brw_reg::subnr, brw_reg::type, brw_reg::ud, brw_instruction::ud, brw_reg::vstride, and brw_reg::width.

00169 {
00170    assert(reg.file != BRW_MESSAGE_REGISTER_FILE);
00171 
00172    insn->bits1.da1.src1_reg_file = reg.file;
00173    insn->bits1.da1.src1_reg_type = reg.type;
00174    insn->bits3.da1.src1_abs = reg.abs;
00175    insn->bits3.da1.src1_negate = reg.negate;
00176 
00177    /* Only src1 can be immediate in two-argument instructions.
00178     */
00179    assert(insn->bits1.da1.src0_reg_file != BRW_IMMEDIATE_VALUE);
00180 
00181    if (reg.file == BRW_IMMEDIATE_VALUE) {
00182       insn->bits3.ud = reg.dw1.ud;
00183    }
00184    else {
00185       /* This is a hardware restriction, which may or may not be lifted
00186        * in the future:
00187        */
00188       assert (reg.address_mode == BRW_ADDRESS_DIRECT);
00189       //assert (reg.file == BRW_GENERAL_REGISTER_FILE);
00190 
00191       if (insn->header.access_mode == BRW_ALIGN_1) {
00192          insn->bits3.da1.src1_subreg_nr = reg.subnr;
00193          insn->bits3.da1.src1_reg_nr = reg.nr;
00194       }
00195       else {
00196          insn->bits3.da16.src1_subreg_nr = reg.subnr / 16;
00197          insn->bits3.da16.src1_reg_nr = reg.nr;
00198       }
00199 
00200       if (insn->header.access_mode == BRW_ALIGN_1) {
00201          if (reg.width == BRW_WIDTH_1 &&
00202              insn->header.execution_size == BRW_EXECUTE_1) {
00203             insn->bits3.da1.src1_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
00204             insn->bits3.da1.src1_width = BRW_WIDTH_1;
00205             insn->bits3.da1.src1_vert_stride = BRW_VERTICAL_STRIDE_0;
00206          }
00207          else {
00208             insn->bits3.da1.src1_horiz_stride = reg.hstride;
00209             insn->bits3.da1.src1_width = reg.width;
00210             insn->bits3.da1.src1_vert_stride = reg.vstride;
00211          }
00212       }
00213       else {
00214          insn->bits3.da16.src1_swz_x = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X);
00215          insn->bits3.da16.src1_swz_y = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y);
00216          insn->bits3.da16.src1_swz_z = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z);
00217          insn->bits3.da16.src1_swz_w = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_W);
00218 
00219          /* This is an oddity of the fact we're using the same
00220           * descriptions for registers in align_16 as align_1:
00221           */
00222          if (reg.vstride == BRW_VERTICAL_STRIDE_8)
00223             insn->bits3.da16.src1_vert_stride = BRW_VERTICAL_STRIDE_4;
00224          else
00225             insn->bits3.da16.src1_vert_stride = reg.vstride;
00226       }
00227    }
00228 }

static __inline struct brw_reg brw_set_writemask	(	struct brw_reg	reg,
		unsigned	mask
	)			`[static, read]`

Definition at line 592 of file brw_eu.h.

References brw_reg::bits, and brw_reg::dw1.

00594 {
00595    reg.dw1.bits.writemask = mask;
00596    return reg;
00597 }

struct brw_instruction* brw_SHL	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 419 of file brw_eu_emit.c.

00440 {

struct brw_instruction* brw_SHR	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 418 of file brw_eu_emit.c.

00440 {

static __inline struct brw_reg brw_swizzle	(	struct brw_reg	reg,
		unsigned	x,
		unsigned	y,
		unsigned	z,
		unsigned	w
	)			`[static, read]`

Definition at line 565 of file brw_eu.h.

References brw_reg::bits, BRW_GET_SWZ, BRW_SWIZZLE4, and brw_reg::dw1.

00570 {
00571    reg.dw1.bits.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(reg.dw1.bits.swizzle, x),
00572                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, y),
00573                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, z),
00574                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, w));
00575    return reg;
00576 }

static __inline struct brw_reg brw_swizzle1	(	struct brw_reg	reg,
		unsigned	x
	)			`[static, read]`

Definition at line 579 of file brw_eu.h.

References brw_swizzle().

00581 {
00582    return brw_swizzle(reg, x, x, x, x);
00583 }

void brw_urb_WRITE	(	struct brw_compile *	p,
		struct brw_reg	dest,
		unsigned	msg_reg_nr,
		struct brw_reg	src0,
		boolean	allocate,
		boolean	used,
		unsigned	msg_length,
		unsigned	response_length,
		boolean	eot,
		boolean	writes_complete,
		unsigned	offset,
		unsigned	swizzle
	)

Definition at line 1047 of file brw_eu_emit.c.

References assert, brw_imm_d(), BRW_OPCODE_SEND, brw_set_dest(), brw_set_src0(), brw_set_src1(), brw_set_urb_message(), brw_instruction::destreg__conditonalmod, brw_instruction::header, and next_insn().

01059 {
01060    struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
01061 
01062    assert(msg_length < 16);
01063 
01064    brw_set_dest(insn, dest);
01065    brw_set_src0(insn, src0);
01066    brw_set_src1(insn, brw_imm_d(0));
01067 
01068    insn->header.destreg__conditonalmod = msg_reg_nr;
01069 
01070    brw_set_urb_message(insn,
01071                        allocate,
01072                        used,
01073                        msg_length,
01074                        response_length,
01075                        eot,
01076                        writes_complete,
01077                        offset,
01078                        swizzle);
01079 }

static __inline struct brw_reg brw_uw16_reg	(	unsigned	file,
		unsigned	nr,
		unsigned	subnr
	)			`[static, read]`

Definition at line 281 of file brw_eu.h.

References BRW_REGISTER_TYPE_UW, brw_vec16_reg(), brw_reg::file, brw_reg::nr, retype(), brw_reg::subnr, and suboffset().

00284 {
00285    return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
00286 }

static __inline struct brw_reg brw_uw1_reg	(	unsigned	file,
		unsigned	nr,
		unsigned	subnr
	)			`[static, read]`

Definition at line 295 of file brw_eu.h.

References BRW_REGISTER_TYPE_UW, brw_vec1_reg(), brw_reg::file, brw_reg::nr, retype(), brw_reg::subnr, and suboffset().

00298 {
00299    return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
00300 }

static __inline struct brw_reg brw_uw8_grf	(	unsigned	nr,
		unsigned	subnr
	)			`[static, read]`

Definition at line 430 of file brw_eu.h.

References BRW_GENERAL_REGISTER_FILE, brw_uw8_reg(), brw_reg::nr, and brw_reg::subnr.

00432 {
00433    return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
00434 }

static __inline struct brw_reg brw_uw8_reg	(	unsigned	file,
		unsigned	nr,
		unsigned	subnr
	)			`[static, read]`

Definition at line 288 of file brw_eu.h.

References BRW_REGISTER_TYPE_UW, brw_vec8_reg(), brw_reg::file, brw_reg::nr, retype(), brw_reg::subnr, and suboffset().

00291 {
00292    return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
00293 }

static __inline struct brw_reg brw_vec16_reg	(	unsigned	file,
		unsigned	nr,
		unsigned	subnr
	)			`[static, read]`

Definition at line 170 of file brw_eu.h.

References BRW_HORIZONTAL_STRIDE_1, brw_reg(), BRW_REGISTER_TYPE_F, BRW_SWIZZLE_XYZW, BRW_VERTICAL_STRIDE_16, BRW_WIDTH_16, brw_reg::file, brw_reg::nr, brw_reg::subnr, and TGSI_WRITEMASK_XYZW.

00173 {
00174    return brw_reg(file,
00175                   nr,
00176                   subnr,
00177                   BRW_REGISTER_TYPE_F,
00178                   BRW_VERTICAL_STRIDE_16,
00179                   BRW_WIDTH_16,
00180                   BRW_HORIZONTAL_STRIDE_1,
00181                   BRW_SWIZZLE_XYZW,
00182                   TGSI_WRITEMASK_XYZW);
00183 }

static __inline struct brw_reg brw_vec1_grf	(	unsigned	nr,
		unsigned	subnr
	)			`[static, read]`

Definition at line 405 of file brw_eu.h.

References BRW_GENERAL_REGISTER_FILE, brw_vec1_reg(), brw_reg::nr, and brw_reg::subnr.

00407 {
00408    return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
00409 }

static __inline struct brw_reg brw_vec1_indirect	(	unsigned	subnr,
		int	offset
	)			`[static, read]`

Definition at line 623 of file brw_eu.h.

References brw_reg::address_mode, brw_reg::bits, BRW_ADDRESS_REGISTER_INDIRECT_REGISTER, brw_vec1_grf(), brw_reg::dw1, offset(), and brw_reg::subnr.

00625 {
00626    struct brw_reg reg =  brw_vec1_grf(0, 0);
00627    reg.subnr = subnr;
00628    reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
00629    reg.dw1.bits.indirect_offset = offset;
00630    return reg;
00631 }

static __inline struct brw_reg brw_vec1_reg	(	unsigned	file,
		unsigned	nr,
		unsigned	subnr
	)			`[static, read]`

Definition at line 232 of file brw_eu.h.

References BRW_HORIZONTAL_STRIDE_0, brw_reg(), BRW_REGISTER_TYPE_F, BRW_SWIZZLE_XXXX, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, brw_reg::file, brw_reg::nr, brw_reg::subnr, and TGSI_WRITEMASK_X.

00235 {
00236    return brw_reg(file,
00237                   nr,
00238                   subnr,
00239                   BRW_REGISTER_TYPE_F,
00240                   BRW_VERTICAL_STRIDE_0,
00241                   BRW_WIDTH_1,
00242                   BRW_HORIZONTAL_STRIDE_0,
00243                   BRW_SWIZZLE_XXXX,
00244                   TGSI_WRITEMASK_X);
00245 }

static __inline struct brw_reg brw_vec2_grf	(	unsigned	nr,
		unsigned	subnr
	)			`[static, read]`

Definition at line 424 of file brw_eu.h.

References BRW_GENERAL_REGISTER_FILE, brw_vec2_reg(), brw_reg::nr, and brw_reg::subnr.

00426 {
00427    return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
00428 }

static __inline struct brw_reg brw_vec2_reg	(	unsigned	file,
		unsigned	nr,
		unsigned	subnr
	)			`[static, read]`

Definition at line 217 of file brw_eu.h.

References BRW_HORIZONTAL_STRIDE_1, brw_reg(), BRW_REGISTER_TYPE_F, BRW_SWIZZLE_XYXY, BRW_VERTICAL_STRIDE_2, BRW_WIDTH_2, brw_reg::file, brw_reg::nr, brw_reg::subnr, and TGSI_WRITEMASK_XY.

00220 {
00221    return brw_reg(file,
00222                   nr,
00223                   subnr,
00224                   BRW_REGISTER_TYPE_F,
00225                   BRW_VERTICAL_STRIDE_2,
00226                   BRW_WIDTH_2,
00227                   BRW_HORIZONTAL_STRIDE_1,
00228                   BRW_SWIZZLE_XYXY,
00229                   TGSI_WRITEMASK_XY);
00230 }

static __inline struct brw_reg brw_vec4_grf	(	unsigned	nr,
		unsigned	subnr
	)			`[static, read]`

Definition at line 417 of file brw_eu.h.

References BRW_GENERAL_REGISTER_FILE, brw_vec4_reg(), brw_reg::nr, and brw_reg::subnr.

00419 {
00420    return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
00421 }

static __inline struct brw_reg brw_vec4_indirect	(	unsigned	subnr,
		int	offset
	)			`[static, read]`

Definition at line 613 of file brw_eu.h.

References brw_reg::address_mode, brw_reg::bits, BRW_ADDRESS_REGISTER_INDIRECT_REGISTER, brw_vec4_grf(), brw_reg::dw1, offset(), and brw_reg::subnr.

00615 {
00616    struct brw_reg reg =  brw_vec4_grf(0, 0);
00617    reg.subnr = subnr;
00618    reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
00619    reg.dw1.bits.indirect_offset = offset;
00620    return reg;
00621 }

static __inline struct brw_reg brw_vec4_reg	(	unsigned	file,
		unsigned	nr,
		unsigned	subnr
	)			`[static, read]`

Definition at line 201 of file brw_eu.h.

References BRW_HORIZONTAL_STRIDE_1, brw_reg(), BRW_REGISTER_TYPE_F, BRW_SWIZZLE_XYZW, BRW_VERTICAL_STRIDE_4, BRW_WIDTH_4, brw_reg::file, brw_reg::nr, brw_reg::subnr, and TGSI_WRITEMASK_XYZW.

00204 {
00205    return brw_reg(file,
00206                   nr,
00207                   subnr,
00208                   BRW_REGISTER_TYPE_F,
00209                   BRW_VERTICAL_STRIDE_4,
00210                   BRW_WIDTH_4,
00211                   BRW_HORIZONTAL_STRIDE_1,
00212                   BRW_SWIZZLE_XYZW,
00213                   TGSI_WRITEMASK_XYZW);
00214 }

static __inline struct brw_reg brw_vec8_grf	(	unsigned	nr,
		unsigned	subnr
	)			`[static, read]`

Definition at line 411 of file brw_eu.h.

References BRW_GENERAL_REGISTER_FILE, brw_vec8_reg(), brw_reg::nr, and brw_reg::subnr.

00413 {
00414    return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
00415 }

static __inline struct brw_reg brw_vec8_reg	(	unsigned	file,
		unsigned	nr,
		unsigned	subnr
	)			`[static, read]`

Definition at line 185 of file brw_eu.h.

References BRW_HORIZONTAL_STRIDE_1, brw_reg(), BRW_REGISTER_TYPE_F, BRW_SWIZZLE_XYZW, BRW_VERTICAL_STRIDE_8, BRW_WIDTH_8, brw_reg::file, brw_reg::nr, brw_reg::subnr, and TGSI_WRITEMASK_XYZW.

00188 {
00189    return brw_reg(file,
00190                   nr,
00191                   subnr,
00192                   BRW_REGISTER_TYPE_F,
00193                   BRW_VERTICAL_STRIDE_8,
00194                   BRW_WIDTH_8,
00195                   BRW_HORIZONTAL_STRIDE_1,
00196                   BRW_SWIZZLE_XYZW,
00197                   TGSI_WRITEMASK_XYZW);
00198 }

struct brw_instruction* brw_WHILE	(	struct brw_compile *	p,
		struct brw_instruction *	patch_insn
	)			`[read]`

Definition at line 655 of file brw_eu_emit.c.

References assert, brw_instruction::bits3, BRW_COMPRESSION_NONE, BRW_EXECUTE_1, brw_imm_d(), brw_ip_reg(), BRW_MASK_DISABLE, BRW_OPCODE_ADD, BRW_OPCODE_DO, BRW_OPCODE_WHILE, BRW_PREDICATE_NONE, brw_set_dest(), brw_set_src0(), brw_set_src1(), brw_instruction::compression_control, brw_compile::current, brw_instruction::d, brw_instruction::execution_size, brw_instruction::header, brw_instruction::if_else, brw_instruction::mask_control, next_insn(), brw_instruction::opcode, brw_instruction::predicate_control, and brw_compile::single_program_flow.

00657 {
00658    struct brw_instruction *insn;
00659 
00660    if (p->single_program_flow)
00661       insn = next_insn(p, BRW_OPCODE_ADD);
00662    else
00663       insn = next_insn(p, BRW_OPCODE_WHILE);
00664 
00665    brw_set_dest(insn, brw_ip_reg());
00666    brw_set_src0(insn, brw_ip_reg());
00667    brw_set_src1(insn, brw_imm_d(0x0));
00668 
00669    insn->header.compression_control = BRW_COMPRESSION_NONE;
00670 
00671    if (p->single_program_flow) {
00672       insn->header.execution_size = BRW_EXECUTE_1;
00673 
00674       insn->bits3.d = (do_insn - insn) * 16;
00675    } else {
00676       insn->header.execution_size = do_insn->header.execution_size;
00677 
00678       assert(do_insn->header.opcode == BRW_OPCODE_DO);
00679       insn->bits3.if_else.jump_count = do_insn - insn;
00680       insn->bits3.if_else.pop_count = 0;
00681       insn->bits3.if_else.pad0 = 0;
00682    }
00683 
00684 /*    insn->header.mask_control = BRW_MASK_ENABLE; */
00685 
00686    insn->header.mask_control = BRW_MASK_DISABLE;
00687    p->current->header.predicate_control = BRW_PREDICATE_NONE;
00688    return insn;
00689 }

static __inline struct brw_reg brw_writemask	(	struct brw_reg	reg,
		unsigned	mask
	)			`[static, read]`

Definition at line 585 of file brw_eu.h.

References brw_reg::bits, and brw_reg::dw1.

00587 {
00588    reg.dw1.bits.writemask &= mask;
00589    return reg;
00590 }

struct brw_instruction* brw_XOR	(	struct brw_compile *	p,
		struct brw_reg	dest,
		struct brw_reg	src0,
		struct brw_reg	src1
	)			`[read]`

Definition at line 417 of file brw_eu_emit.c.

00440 {

static __inline struct brw_reg byte_offset	(	struct brw_reg	reg,
		unsigned	bytes
	)			`[static, read]`

Definition at line 271 of file brw_eu.h.

References brw_reg::nr, and REG_SIZE.

00273 {
00274    unsigned newoffset = reg.nr * REG_SIZE + reg.subnr + bytes;
00275    reg.nr = newoffset / REG_SIZE;
00276    reg.subnr = newoffset % REG_SIZE;
00277    return reg;
00278 }

static __inline struct brw_instruction* current_insn ( struct brw_compile * p ) [static, read]

Definition at line 678 of file brw_eu.h.

References brw_compile::nr_insn, and brw_compile::store.

00679 {
00680         return &p->store[p->nr_insn];
00681 }

static __inline unsigned cvt ( unsigned val ) [static]

Definition at line 503 of file brw_eu.h.

00504 {
00505    switch (val) {
00506    case 0: return 0;
00507    case 1: return 1;
00508    case 2: return 2;
00509    case 4: return 3;
00510    case 8: return 4;
00511    case 16: return 5;
00512    case 32: return 6;
00513    }
00514    return 0;
00515 }

static __inline struct brw_reg deref_1f	(	struct brw_indirect	ptr,
		int	offset
	)			`[static, read]`

Definition at line 638 of file brw_eu.h.

References brw_vec1_indirect(), and offset().

00639 {
00640    return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
00641 }

static __inline struct brw_reg deref_1ud	(	struct brw_indirect	ptr,
		int	offset
	)			`[static, read]`

Definition at line 653 of file brw_eu.h.

References BRW_REGISTER_TYPE_UD, deref_1f(), offset(), and retype().

00654 {
00655    return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD);
00656 }

static __inline struct brw_reg deref_1uw	(	struct brw_indirect	ptr,
		int	offset
	)			`[static, read]`

Definition at line 648 of file brw_eu.h.

References BRW_REGISTER_TYPE_UW, deref_1f(), offset(), and retype().

00649 {
00650    return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW);
00651 }

static __inline struct brw_reg deref_4b	(	struct brw_indirect	ptr,
		int	offset
	)			`[static, read]`

Definition at line 643 of file brw_eu.h.

References BRW_REGISTER_TYPE_B, deref_4f(), offset(), and retype().

00644 {
00645    return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B);
00646 }

static __inline struct brw_reg deref_4f	(	struct brw_indirect	ptr,
		int	offset
	)			`[static, read]`

Definition at line 633 of file brw_eu.h.

References brw_vec4_indirect(), and offset().

00634 {
00635    return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
00636 }

static __inline struct brw_reg get_addr_reg ( struct brw_indirect ptr ) [static, read]

Definition at line 658 of file brw_eu.h.

References brw_address_reg().

00659 {
00660    return brw_address_reg(ptr.addr_subnr);
00661 }

static __inline struct brw_reg get_element	(	struct brw_reg	reg,
		unsigned	elt
	)			`[static, read]`

Definition at line 554 of file brw_eu.h.

References suboffset(), and vec1().

00555 {
00556    return vec1(suboffset(reg, elt));
00557 }

static __inline struct brw_reg get_element_ud	(	struct brw_reg	reg,
		unsigned	elt
	)			`[static, read]`

Definition at line 559 of file brw_eu.h.

References BRW_REGISTER_TYPE_UD, retype(), suboffset(), and vec1().

00560 {
00561    return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt));
00562 }

static __inline struct brw_reg negate ( struct brw_reg reg ) [static, read]

Definition at line 599 of file brw_eu.h.

00600 {
00601    reg.negate ^= 1;
00602    return reg;
00603 }

static __inline struct brw_reg offset	(	struct brw_reg	reg,
		unsigned	delta
	)			`[static, read]`

Definition at line 263 of file brw_eu.h.

References brw_reg::nr.

00265 {
00266    reg.nr += delta;
00267    return reg;
00268 }

static __inline struct brw_reg retype	(	struct brw_reg	reg,
		unsigned	type
	)			`[static, read]`

Definition at line 248 of file brw_eu.h.

References brw_reg::type.

00250 {
00251    reg.type = type;
00252    return reg;
00253 }

static __inline struct brw_reg stride	(	struct brw_reg	reg,
		unsigned	vstride,
		unsigned	width,
		unsigned	hstride
	)			`[static, read]`

Definition at line 517 of file brw_eu.h.

References cvt(), brw_reg::hstride, brw_reg::vstride, and brw_reg::width.

00521 {
00522 
00523    reg.vstride = cvt(vstride);
00524    reg.width = cvt(width) - 1;
00525    reg.hstride = cvt(hstride);
00526    return reg;
00527 }

static __inline struct brw_reg suboffset	(	struct brw_reg	reg,
		unsigned	delta
	)			`[static, read]`

Definition at line 255 of file brw_eu.h.

References brw_reg::subnr, and type_sz().

00257 {
00258    reg.subnr += delta * type_sz(reg.type);
00259    return reg;
00260 }

static __inline int type_sz ( unsigned type ) [static]

Definition at line 114 of file brw_eu.h.

References BRW_REGISTER_TYPE_B, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_HF, BRW_REGISTER_TYPE_UB, BRW_REGISTER_TYPE_UD, BRW_REGISTER_TYPE_UW, and BRW_REGISTER_TYPE_W.

00115 {
00116    switch( type ) {
00117    case BRW_REGISTER_TYPE_UD:
00118    case BRW_REGISTER_TYPE_D:
00119    case BRW_REGISTER_TYPE_F:
00120       return 4;
00121    case BRW_REGISTER_TYPE_HF:
00122    case BRW_REGISTER_TYPE_UW:
00123    case BRW_REGISTER_TYPE_W:
00124       return 2;
00125    case BRW_REGISTER_TYPE_UB:
00126    case BRW_REGISTER_TYPE_B:
00127       return 1;
00128    default:
00129       return 0;
00130    }
00131 }

static __inline struct brw_reg vec1 ( struct brw_reg reg ) [static, read]

Definition at line 549 of file brw_eu.h.

References stride().

00550 {
00551    return stride(reg, 0,1,0);
00552 }

static __inline struct brw_reg vec16 ( struct brw_reg reg ) [static, read]

Definition at line 529 of file brw_eu.h.

References stride().

00530 {
00531    return stride(reg, 16,16,1);
00532 }

static __inline struct brw_reg vec2 ( struct brw_reg reg ) [static, read]

Definition at line 544 of file brw_eu.h.

References stride().

00545 {
00546    return stride(reg, 2,2,1);
00547 }

static __inline struct brw_reg vec4 ( struct brw_reg reg ) [static, read]

Definition at line 539 of file brw_eu.h.

References stride().

00540 {
00541    return stride(reg, 4,4,1);
00542 }

static __inline struct brw_reg vec8 ( struct brw_reg reg ) [static, read]

Definition at line 534 of file brw_eu.h.

References stride().

00535 {
00536    return stride(reg, 8,8,1);
00537 }

brw_eu.h File Reference

Data Structures

Defines

Functions

Define Documentation

Function Documentation


Data Structures
struct	brw_reg
struct	brw_indirect
struct	brw_compile
Defines
#define	BRW_SWIZZLE4(a, b, c, d) (((a)<<0) \| ((b)<<2) \| ((c)<<4) \| ((d)<<6))
#define	BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
#define	BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
#define	BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
#define	BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
#define	BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
#define	REG_SIZE (8*4)
#define	BRW_EU_MAX_INSN_STACK 5
#define	BRW_EU_MAX_INSN 1200
#define	VF_ZERO 0x0
#define	VF_ONE 0x30
#define	VF_NEG (1<<7)
#define	ALU1(OP)
#define	ALU2(OP)
Functions
static __inline int	type_sz (unsigned type)
static __inline struct brw_reg	brw_reg (unsigned file, unsigned nr, unsigned subnr, unsigned type, unsigned vstride, unsigned width, unsigned hstride, unsigned swizzle, unsigned writemask)
static __inline struct brw_reg	brw_vec16_reg (unsigned file, unsigned nr, unsigned subnr)
static __inline struct brw_reg	brw_vec8_reg (unsigned file, unsigned nr, unsigned subnr)
static __inline struct brw_reg	brw_vec4_reg (unsigned file, unsigned nr, unsigned subnr)
static __inline struct brw_reg	brw_vec2_reg (unsigned file, unsigned nr, unsigned subnr)
static __inline struct brw_reg	brw_vec1_reg (unsigned file, unsigned nr, unsigned subnr)
static __inline struct brw_reg	retype (struct brw_reg reg, unsigned type)
static __inline struct brw_reg	suboffset (struct brw_reg reg, unsigned delta)
static __inline struct brw_reg	offset (struct brw_reg reg, unsigned delta)
static __inline struct brw_reg	byte_offset (struct brw_reg reg, unsigned bytes)
static __inline struct brw_reg	brw_uw16_reg (unsigned file, unsigned nr, unsigned subnr)
static __inline struct brw_reg	brw_uw8_reg (unsigned file, unsigned nr, unsigned subnr)
static __inline struct brw_reg	brw_uw1_reg (unsigned file, unsigned nr, unsigned subnr)
static __inline struct brw_reg	brw_imm_reg (unsigned type)
static __inline struct brw_reg	brw_imm_f (float f)
static __inline struct brw_reg	brw_imm_d (int d)
static __inline struct brw_reg	brw_imm_ud (unsigned ud)
static __inline struct brw_reg	brw_imm_uw (ushort uw)
static __inline struct brw_reg	brw_imm_w (short w)
static __inline struct brw_reg	brw_imm_v (unsigned v)
static __inline struct brw_reg	brw_imm_vf (unsigned v)
static __inline struct brw_reg	brw_imm_vf4 (unsigned v0, unsigned v1, unsigned v2, unsigned v3)
static __inline struct brw_reg	brw_address (struct brw_reg reg)
static __inline struct brw_reg	brw_vec1_grf (unsigned nr, unsigned subnr)
static __inline struct brw_reg	brw_vec8_grf (unsigned nr, unsigned subnr)
static __inline struct brw_reg	brw_vec4_grf (unsigned nr, unsigned subnr)
static __inline struct brw_reg	brw_vec2_grf (unsigned nr, unsigned subnr)
static __inline struct brw_reg	brw_uw8_grf (unsigned nr, unsigned subnr)
static __inline struct brw_reg	brw_null_reg (void)
static __inline struct brw_reg	brw_address_reg (unsigned subnr)
static __inline struct brw_reg	brw_ip_reg (void)
static __inline struct brw_reg	brw_acc_reg (void)
static __inline struct brw_reg	brw_flag_reg (void)
static __inline struct brw_reg	brw_mask_reg (unsigned subnr)
static __inline struct brw_reg	brw_message_reg (unsigned nr)
static __inline unsigned	cvt (unsigned val)
static __inline struct brw_reg	stride (struct brw_reg reg, unsigned vstride, unsigned width, unsigned hstride)
static __inline struct brw_reg	vec16 (struct brw_reg reg)
static __inline struct brw_reg	vec8 (struct brw_reg reg)
static __inline struct brw_reg	vec4 (struct brw_reg reg)
static __inline struct brw_reg	vec2 (struct brw_reg reg)
static __inline struct brw_reg	vec1 (struct brw_reg reg)
static __inline struct brw_reg	get_element (struct brw_reg reg, unsigned elt)
static __inline struct brw_reg	get_element_ud (struct brw_reg reg, unsigned elt)
static __inline struct brw_reg	brw_swizzle (struct brw_reg reg, unsigned x, unsigned y, unsigned z, unsigned w)
static __inline struct brw_reg	brw_swizzle1 (struct brw_reg reg, unsigned x)
static __inline struct brw_reg	brw_writemask (struct brw_reg reg, unsigned mask)
static __inline struct brw_reg	brw_set_writemask (struct brw_reg reg, unsigned mask)
static __inline struct brw_reg	negate (struct brw_reg reg)
static __inline struct brw_reg	brw_abs (struct brw_reg reg)
static __inline struct brw_reg	brw_vec4_indirect (unsigned subnr, int offset)
static __inline struct brw_reg	brw_vec1_indirect (unsigned subnr, int offset)
static __inline struct brw_reg	deref_4f (struct brw_indirect ptr, int offset)
static __inline struct brw_reg	deref_1f (struct brw_indirect ptr, int offset)
static __inline struct brw_reg	deref_4b (struct brw_indirect ptr, int offset)
static __inline struct brw_reg	deref_1uw (struct brw_indirect ptr, int offset)
static __inline struct brw_reg	deref_1ud (struct brw_indirect ptr, int offset)
static __inline struct brw_reg	get_addr_reg (struct brw_indirect ptr)
static __inline struct brw_indirect	brw_indirect_offset (struct brw_indirect ptr, int offset)
static __inline struct brw_indirect	brw_indirect (unsigned addr_subnr, int offset)
static __inline struct brw_instruction *	current_insn (struct brw_compile *p)
void	brw_pop_insn_state (struct brw_compile *p)
void	brw_push_insn_state (struct brw_compile *p)
void	brw_set_mask_control (struct brw_compile *p, unsigned value)
void	brw_set_saturate (struct brw_compile *p, unsigned value)
void	brw_set_access_mode (struct brw_compile *p, unsigned access_mode)
void	brw_set_compression_control (struct brw_compile *p, boolean control)
void	brw_set_predicate_control_flag_value (struct brw_compile *p, unsigned value)
void	brw_set_predicate_control (struct brw_compile *p, unsigned pc)
void	brw_set_conditionalmod (struct brw_compile *p, unsigned conditional)
void	brw_init_compile (struct brw_compile *p)
const unsigned *	brw_get_program (struct brw_compile p, unsigned sz)
struct brw_instruction *	brw_alu1 (struct brw_compile *p, unsigned opcode, struct brw_reg dest, struct brw_reg src)
struct brw_instruction *	brw_alu2 (struct brw_compile *p, unsigned opcode, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_MOV (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0)
struct brw_instruction *	brw_SEL (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_NOT (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0)
struct brw_instruction *	brw_AND (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_OR (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_XOR (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_SHR (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_SHL (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_RSR (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_RSL (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_ASR (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_JMPI (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_ADD (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_MUL (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_FRC (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0)
struct brw_instruction *	brw_RNDD (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0)
struct brw_instruction *	brw_MAC (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_MACH (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_LZD (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0)
struct brw_instruction *	brw_DP4 (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_DPH (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_DP3 (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_DP2 (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
struct brw_instruction *	brw_LINE (struct brw_compile *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
void	brw_urb_WRITE (struct brw_compile *p, struct brw_reg dest, unsigned msg_reg_nr, struct brw_reg src0, boolean allocate, boolean used, unsigned msg_length, unsigned response_length, boolean eot, boolean writes_complete, unsigned offset, unsigned swizzle)
void	brw_fb_WRITE (struct brw_compile *p, struct brw_reg dest, unsigned msg_reg_nr, struct brw_reg src0, unsigned binding_table_index, unsigned msg_length, unsigned response_length, boolean eot)
void	brw_SAMPLE (struct brw_compile *p, struct brw_reg dest, unsigned msg_reg_nr, struct brw_reg src0, unsigned binding_table_index, unsigned sampler, unsigned writemask, unsigned msg_type, unsigned response_length, unsigned msg_length, boolean eot)
void	brw_math_16 (struct brw_compile *p, struct brw_reg dest, unsigned function, unsigned saturate, unsigned msg_reg_nr, struct brw_reg src, unsigned precision)
void	brw_math (struct brw_compile *p, struct brw_reg dest, unsigned function, unsigned saturate, unsigned msg_reg_nr, struct brw_reg src, unsigned data_type, unsigned precision)
void	brw_dp_READ_16 (struct brw_compile *p, struct brw_reg dest, unsigned msg_reg_nr, unsigned scratch_offset)
void	brw_dp_WRITE_16 (struct brw_compile *p, struct brw_reg src, unsigned msg_reg_nr, unsigned scratch_offset)
struct brw_instruction *	brw_IF (struct brw_compile *p, unsigned execute_size)
struct brw_instruction *	brw_ELSE (struct brw_compile p, struct brw_instruction if_insn)
void	brw_ENDIF (struct brw_compile p, struct brw_instruction if_or_else_insn)
struct brw_instruction *	brw_DO (struct brw_compile *p, unsigned execute_size)
struct brw_instruction *	brw_WHILE (struct brw_compile p, struct brw_instruction patch_insn)
struct brw_instruction *	brw_BREAK (struct brw_compile *p)
struct brw_instruction *	brw_CONT (struct brw_compile *p)
void	brw_land_fwd_jump (struct brw_compile p, struct brw_instruction jmp_insn)
void	brw_NOP (struct brw_compile *p)
void	brw_CMP (struct brw_compile *p, struct brw_reg dest, unsigned conditional, struct brw_reg src0, struct brw_reg src1)
void	brw_print_reg (struct brw_reg reg)
void	brw_copy_indirect_to_indirect (struct brw_compile *p, struct brw_indirect dst_ptr, struct brw_indirect src_ptr, unsigned count)
void	brw_copy_from_indirect (struct brw_compile *p, struct brw_reg dst, struct brw_indirect ptr, unsigned count)
void	brw_copy4 (struct brw_compile *p, struct brw_reg dst, struct brw_reg src, unsigned count)
void	brw_copy8 (struct brw_compile *p, struct brw_reg dst, struct brw_reg src, unsigned count)
void	brw_math_invert (struct brw_compile *p, struct brw_reg dst, struct brw_reg src)
void	brw_set_src1 (struct brw_instruction *insn, struct brw_reg reg)