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| static void upload_binding_table_pointers | ( | struct brw_context * | brw | ) | [static] |
Upload the binding table pointers, which point each stage's array of surface state pointers.
The binding table pointers are relative to the surface state base address, which is the BRW_SS_POOL cache buffer.
Definition at line 108 of file brw_misc_state.c.
References brw_context::bind_ss_offset, BRW_CACHED_BATCH_STRUCT, brw_binding_table_pointers::clp, CMD_BINDING_TABLE_PTRS, brw_binding_table_pointers::gs, brw_binding_table_pointers::header, header::length, header::opcode, brw_binding_table_pointers::sf, brw_binding_table_pointers::vs, brw_context::wm, and brw_binding_table_pointers::wm.
00109 { 00110 struct brw_binding_table_pointers btp; 00111 memset(&btp, 0, sizeof(btp)); 00112 00113 btp.header.opcode = CMD_BINDING_TABLE_PTRS; 00114 btp.header.length = sizeof(btp)/4 - 2; 00115 btp.vs = 0; 00116 btp.gs = 0; 00117 btp.clp = 0; 00118 btp.sf = 0; 00119 btp.wm = brw->wm.bind_ss_offset; 00120 00121 BRW_CACHED_BATCH_STRUCT(brw, &btp); 00122 }
| static void upload_blend_constant_color | ( | struct brw_context * | brw | ) | [static] |
Definition at line 45 of file brw_misc_state.c.
References brw_context::attribs, brw_blend_constant_color::blend_constant_color, brw_context::BlendColor, BRW_CACHED_BATCH_STRUCT, CMD_BLEND_CONSTANT_COLOR, pipe_blend_color::color, brw_blend_constant_color::header, header::length, and header::opcode.
00046 { 00047 struct brw_blend_constant_color bcc; 00048 00049 memset(&bcc, 0, sizeof(bcc)); 00050 bcc.header.opcode = CMD_BLEND_CONSTANT_COLOR; 00051 bcc.header.length = sizeof(bcc)/4-2; 00052 bcc.blend_constant_color[0] = brw->attribs.BlendColor.color[0]; 00053 bcc.blend_constant_color[1] = brw->attribs.BlendColor.color[1]; 00054 bcc.blend_constant_color[2] = brw->attribs.BlendColor.color[2]; 00055 bcc.blend_constant_color[3] = brw->attribs.BlendColor.color[3]; 00056 00057 BRW_CACHED_BATCH_STRUCT(brw, &bcc); 00058 }
| static void upload_depthbuffer | ( | struct brw_context * | brw | ) | [static] |
Upload the depthbuffer offset and format.
We have to do this per state validation as we need to emit the relocation in the batch buffer.
Definition at line 212 of file brw_misc_state.c.
References ADVANCE_BATCH, assert, brw_context::attribs, BEGIN_BATCH, pipe_surface::block, BRW_DEPTHFORMAT_D16_UNORM, BRW_DEPTHFORMAT_D24_UNORM_S8_UINT, BRW_DEPTHFORMAT_D32_FLOAT, BRW_SURFACE_2D, BRW_SURFACE_MIPMAPLAYOUT_BELOW, BRW_SURFACE_NULL, BRW_TILEWALK_YMAJOR, pipe_surface::buffer, CMD_DEPTH_BUFFER, pipe_surface::format, brw_context::FrameBuffer, pipe_surface::height, pipe_format_block::height, INTEL_BATCH_NO_CLIPRECTS, OUT_BATCH, OUT_RELOC, PIPE_BUFFER_USAGE_GPU_READ, PIPE_BUFFER_USAGE_GPU_WRITE, PIPE_FORMAT_Z32_FLOAT, pipe_format_block::size, pipe_surface::stride, pipe_format_block::width, and pipe_framebuffer_state::zsbuf.
00213 { 00214 struct pipe_surface *depth_surface = brw->attribs.FrameBuffer.zsbuf; 00215 00216 BEGIN_BATCH(5, INTEL_BATCH_NO_CLIPRECTS); 00217 OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (5 - 2)); 00218 if (depth_surface == NULL) { 00219 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | 00220 (BRW_SURFACE_NULL << 29)); 00221 OUT_BATCH(0); 00222 OUT_BATCH(0); 00223 OUT_BATCH(0); 00224 } else { 00225 unsigned int format; 00226 00227 assert(depth_surface->block.width == 1); 00228 assert(depth_surface->block.height == 1); 00229 switch (depth_surface->block.size) { 00230 case 2: 00231 format = BRW_DEPTHFORMAT_D16_UNORM; 00232 break; 00233 case 4: 00234 if (depth_surface->format == PIPE_FORMAT_Z32_FLOAT) 00235 format = BRW_DEPTHFORMAT_D32_FLOAT; 00236 else 00237 format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT; 00238 break; 00239 default: 00240 assert(0); 00241 return; 00242 } 00243 00244 OUT_BATCH((depth_surface->stride - 1) | 00245 (format << 18) | 00246 (BRW_TILEWALK_YMAJOR << 26) | 00247 // (depth_surface->region->tiled << 27) | 00248 (BRW_SURFACE_2D << 29)); 00249 OUT_RELOC(depth_surface->buffer, 00250 PIPE_BUFFER_USAGE_GPU_READ | PIPE_BUFFER_USAGE_GPU_WRITE, 0); 00251 OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) | 00252 ((depth_surface->stride/depth_surface->block.size - 1) << 6) | 00253 ((depth_surface->height - 1) << 19)); 00254 OUT_BATCH(0); 00255 } 00256 ADVANCE_BATCH(); 00257 }
| static void upload_drawing_rect | ( | struct brw_context * | brw | ) | [static] |
Definition at line 73 of file brw_misc_state.c.
References brw_context::attribs, BRW_BATCH_STRUCT, pipe_framebuffer_state::cbufs, CMD_DRAW_RECT, brw_context::FrameBuffer, brw_drawrect::header, pipe_surface::height, header::length, header::opcode, pipe_surface::width, brw_drawrect::xmax, brw_drawrect::xmin, brw_drawrect::xorg, brw_drawrect::ymax, brw_drawrect::ymin, and brw_drawrect::yorg.
00074 { 00075 struct brw_drawrect bdr; 00076 00077 memset(&bdr, 0, sizeof(bdr)); 00078 bdr.header.opcode = CMD_DRAW_RECT; 00079 bdr.header.length = sizeof(bdr)/4 - 2; 00080 bdr.xmin = 0; 00081 bdr.ymin = 0; 00082 bdr.xmax = brw->attribs.FrameBuffer.cbufs[0]->width; 00083 bdr.ymax = brw->attribs.FrameBuffer.cbufs[0]->height; 00084 bdr.xorg = 0; 00085 bdr.yorg = 0; 00086 00087 /* Can't use BRW_CACHED_BATCH_STRUCT because this is also emitted 00088 * uncached in brw_draw.c: 00089 */ 00090 BRW_BATCH_STRUCT(brw, &bdr); 00091 }
| static void upload_invarient_state | ( | struct brw_context * | brw | ) | [static] |
Definition at line 372 of file brw_misc_state.c.
References brw_polygon_stipple_offset::bits0, brw_system_instruction_pointer::bits0, BRW_BATCH_STRUCT, BRW_DEBUG, BRW_FLUSH_READ_CACHE, BRW_FLUSH_STATE_CACHE, CMD_GLOBAL_DEPTH_OFFSET_CLAMP, CMD_MI_FLUSH, CMD_PIPELINE_SELECT, CMD_POLY_STIPPLE_OFFSET, CMD_STATE_INSN_POINTER, CMD_VF_STATISTICS, DEBUG_STATS, brw_global_depth_offset_clamp::depth_offset_clamp, brw_mi_flush::flags, brw_polygon_stipple_offset::header, brw_system_instruction_pointer::header, brw_global_depth_offset_clamp::header, brw_pipeline_select::header, header::length, brw_vf_statistics::opcode, header::opcode, brw_pipeline_select::opcode, brw_mi_flush::opcode, brw_system_instruction_pointer::pad, brw_pipeline_select::pipeline_select, brw_vf_statistics::statistics_enable, brw_system_instruction_pointer::system_instruction_pointer, brw_polygon_stipple_offset::x_offset, and brw_polygon_stipple_offset::y_offset.
00373 { 00374 { 00375 struct brw_mi_flush flush; 00376 00377 memset(&flush, 0, sizeof(flush)); 00378 flush.opcode = CMD_MI_FLUSH; 00379 flush.flags = BRW_FLUSH_STATE_CACHE | BRW_FLUSH_READ_CACHE; 00380 BRW_BATCH_STRUCT(brw, &flush); 00381 } 00382 00383 { 00384 /* 0x61040000 Pipeline Select */ 00385 /* PipelineSelect : 0 */ 00386 struct brw_pipeline_select ps; 00387 00388 memset(&ps, 0, sizeof(ps)); 00389 ps.header.opcode = CMD_PIPELINE_SELECT; 00390 ps.header.pipeline_select = 0; 00391 BRW_BATCH_STRUCT(brw, &ps); 00392 } 00393 00394 { 00395 struct brw_global_depth_offset_clamp gdo; 00396 memset(&gdo, 0, sizeof(gdo)); 00397 00398 /* Disable depth offset clamping. 00399 */ 00400 gdo.header.opcode = CMD_GLOBAL_DEPTH_OFFSET_CLAMP; 00401 gdo.header.length = sizeof(gdo)/4 - 2; 00402 gdo.depth_offset_clamp = 0.0; 00403 00404 BRW_BATCH_STRUCT(brw, &gdo); 00405 } 00406 00407 00408 /* 0x61020000 State Instruction Pointer */ 00409 { 00410 struct brw_system_instruction_pointer sip; 00411 memset(&sip, 0, sizeof(sip)); 00412 00413 sip.header.opcode = CMD_STATE_INSN_POINTER; 00414 sip.header.length = 0; 00415 sip.bits0.pad = 0; 00416 sip.bits0.system_instruction_pointer = 0; 00417 BRW_BATCH_STRUCT(brw, &sip); 00418 } 00419 00420 00421 { 00422 struct brw_vf_statistics vfs; 00423 memset(&vfs, 0, sizeof(vfs)); 00424 00425 vfs.opcode = CMD_VF_STATISTICS; 00426 if (BRW_DEBUG & DEBUG_STATS) 00427 vfs.statistics_enable = 1; 00428 00429 BRW_BATCH_STRUCT(brw, &vfs); 00430 } 00431 00432 00433 { 00434 struct brw_polygon_stipple_offset bpso; 00435 00436 memset(&bpso, 0, sizeof(bpso)); 00437 bpso.header.opcode = CMD_POLY_STIPPLE_OFFSET; 00438 bpso.header.length = sizeof(bpso)/4-2; 00439 bpso.bits0.x_offset = 0; 00440 bpso.bits0.y_offset = 0; 00441 00442 BRW_BATCH_STRUCT(brw, &bpso); 00443 } 00444 }
| static void upload_line_stipple | ( | struct brw_context * | brw | ) | [static] |
Definition at line 305 of file brw_misc_state.c.
References brw_context::attribs, brw_line_stipple::bits0, brw_line_stipple::bits1, BRW_CACHED_BATCH_STRUCT, CMD_LINE_STIPPLE_PATTERN, brw_line_stipple::header, brw_line_stipple::inverse_repeat_count, header::length, pipe_rasterizer_state::line_stipple_factor, pipe_rasterizer_state::line_stipple_pattern, header::opcode, brw_line_stipple::pattern, brw_context::Raster, and brw_line_stipple::repeat_count.
00306 { 00307 struct brw_line_stipple bls; 00308 float tmp; 00309 int tmpi; 00310 00311 memset(&bls, 0, sizeof(bls)); 00312 bls.header.opcode = CMD_LINE_STIPPLE_PATTERN; 00313 bls.header.length = sizeof(bls)/4 - 2; 00314 00315 bls.bits0.pattern = brw->attribs.Raster->line_stipple_pattern; 00316 bls.bits1.repeat_count = brw->attribs.Raster->line_stipple_factor; 00317 00318 tmp = 1.0 / (float) brw->attribs.Raster->line_stipple_factor; 00319 tmpi = tmp * (1<<13); 00320 00321 00322 bls.bits1.inverse_repeat_count = tmpi; 00323 00324 BRW_CACHED_BATCH_STRUCT(brw, &bls); 00325 }
| static void upload_pipe_control | ( | struct brw_context * | brw | ) | [static] |
Definition at line 340 of file brw_misc_state.c.
References brw_pipe_control::bits1, BRW_BATCH_STRUCT, CMD_PIPE_CONTROL, brw_pipe_control::dest_addr_type, brw_pipe_control::header, brw_pipe_control::instruction_state_cache_flush_enable, brw_pipe_control::length, brw_pipe_control::opcode, PIPE_CONTROL_GTTWRITE_GLOBAL, PIPE_CONTROL_NOWRITE, and brw_pipe_control::post_sync_operation.
00341 { 00342 struct brw_pipe_control pc; 00343 00344 return; 00345 00346 memset(&pc, 0, sizeof(pc)); 00347 00348 pc.header.opcode = CMD_PIPE_CONTROL; 00349 pc.header.length = sizeof(pc)/4 - 2; 00350 pc.header.post_sync_operation = PIPE_CONTROL_NOWRITE; 00351 00352 pc.header.instruction_state_cache_flush_enable = 1; 00353 00354 pc.bits1.dest_addr_type = PIPE_CONTROL_GTTWRITE_GLOBAL; 00355 00356 BRW_BATCH_STRUCT(brw, &pc); 00357 }
| static void upload_pipelined_state_pointers | ( | struct brw_context * | brw | ) | [static] |
Upload pointers to the per-stage state.
The state pointers in this packet are all relative to the general state base address set by CMD_STATE_BASE_ADDRESS, which is the BRW_GS_POOL buffer.
Definition at line 139 of file brw_misc_state.c.
References brw_state_flags::brw, BRW_CACHED_BATCH_STRUCT, BRW_NEW_PSP, brw_context::cc, brw_pipelined_state_pointers::cc, brw_context::clip, brw_pipelined_state_pointers::clp, CMD_PIPELINED_STATE_POINTERS, brw_context::dirty, brw_pipelined_state_pointers::enable, brw_pipelined_state_pointers::gs, brw_context::gs, brw_pipelined_state_pointers::header, header::length, brw_pipelined_state_pointers::offset, header::opcode, brw_context::prog_active, brw_context::sf, brw_pipelined_state_pointers::sf, brw_context::state, brw_context::state_gs_offset, brw_context::vs, brw_pipelined_state_pointers::vs, brw_context::wm, and brw_pipelined_state_pointers::wm.
00140 { 00141 struct brw_pipelined_state_pointers psp; 00142 memset(&psp, 0, sizeof(psp)); 00143 00144 psp.header.opcode = CMD_PIPELINED_STATE_POINTERS; 00145 psp.header.length = sizeof(psp)/4 - 2; 00146 00147 psp.vs.offset = brw->vs.state_gs_offset >> 5; 00148 psp.sf.offset = brw->sf.state_gs_offset >> 5; 00149 psp.wm.offset = brw->wm.state_gs_offset >> 5; 00150 psp.cc.offset = brw->cc.state_gs_offset >> 5; 00151 00152 /* GS gets turned on and off regularly. Need to re-emit URB fence 00153 * after this occurs. 00154 */ 00155 if (brw->gs.prog_active) { 00156 psp.gs.offset = brw->gs.state_gs_offset >> 5; 00157 psp.gs.enable = 1; 00158 } 00159 00160 if (0) { 00161 psp.clp.offset = brw->clip.state_gs_offset >> 5; 00162 psp.clp.enable = 1; 00163 } 00164 00165 00166 if (BRW_CACHED_BATCH_STRUCT(brw, &psp)) 00167 brw->state.dirty.brw |= BRW_NEW_PSP; 00168 }
| static void upload_polygon_stipple | ( | struct brw_context * | brw | ) | [static] |
Definition at line 274 of file brw_misc_state.c.
References brw_context::attribs, BRW_CACHED_BATCH_STRUCT, CMD_POLY_STIPPLE_PATTERN, brw_polygon_stipple::header, header::length, header::opcode, brw_context::PolygonStipple, pipe_poly_stipple::stipple, and brw_polygon_stipple::stipple.
00275 { 00276 struct brw_polygon_stipple bps; 00277 unsigned i; 00278 00279 memset(&bps, 0, sizeof(bps)); 00280 bps.header.opcode = CMD_POLY_STIPPLE_PATTERN; 00281 bps.header.length = sizeof(bps)/4-2; 00282 00283 /* XXX: state tracker should send *all* state down initially! 00284 */ 00285 if (brw->attribs.PolygonStipple) 00286 for (i = 0; i < 32; i++) 00287 bps.stipple[i] = brw->attribs.PolygonStipple->stipple[31 - i]; /* invert */ 00288 00289 BRW_CACHED_BATCH_STRUCT(brw, &bps); 00290 }
| static void upload_psp_urb_cbs | ( | struct brw_context * | brw | ) | [static] |
Definition at line 184 of file brw_misc_state.c.
References brw_upload_constant_buffer_state(), brw_upload_urb_fence(), and upload_pipelined_state_pointers().
00185 { 00186 upload_pipelined_state_pointers(brw); 00187 brw_upload_urb_fence(brw); 00188 brw_upload_constant_buffer_state(brw); 00189 }
| static void upload_state_base_address | ( | struct brw_context * | brw | ) | [static] |
Define the base addresses which some state is referenced from.
This allows us to avoid having to emit relocations in many places for cached state, and instead emit pointers inside of large, mostly-static state pools. This comes at the expense of memory, and more expensive cache misses.
Definition at line 462 of file brw_misc_state.c.
References ADVANCE_BATCH, BEGIN_BATCH, BRW_GS_POOL, BRW_SS_POOL, brw_mem_pool::buffer, CMD_STATE_BASE_ADDRESS, INTEL_BATCH_NO_CLIPRECTS, OUT_BATCH, OUT_RELOC, PIPE_BUFFER_USAGE_GPU_READ, and brw_context::pool.
00463 { 00464 /* Output the structure (brw_state_base_address) directly to the 00465 * batchbuffer, so we can emit relocations inline. 00466 */ 00467 BEGIN_BATCH(6, INTEL_BATCH_NO_CLIPRECTS); 00468 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2)); 00469 OUT_RELOC(brw->pool[BRW_GS_POOL].buffer, 00470 PIPE_BUFFER_USAGE_GPU_READ, 00471 1); /* General state base address */ 00472 OUT_RELOC(brw->pool[BRW_SS_POOL].buffer, 00473 PIPE_BUFFER_USAGE_GPU_READ, 00474 1); /* Surface state base address */ 00475 OUT_BATCH(1); /* Indirect object base address */ 00476 OUT_BATCH(1); /* General state upper bound */ 00477 OUT_BATCH(1); /* Indirect object upper bound */ 00478 ADVANCE_BATCH(); 00479 }
Initial value:
{
.dirty = {
.brw = 0,
.cache = (1<<BRW_SS_SURF_BIND)
},
.update = upload_binding_table_pointers,
}
Definition at line 124 of file brw_misc_state.c.
Initial value:
{
.dirty = {
.brw = 0x8 ,
.cache = 0
},
.update = upload_blend_constant_color
}
Definition at line 61 of file brw_misc_state.c.
| struct brw_tracked_state brw_depthbuffer |
Initial value:
{
.dirty = {
.brw = 0x200000 ,
.cache = 0
},
.update = upload_depthbuffer,
}
Definition at line 259 of file brw_misc_state.c.
Initial value:
{
.dirty = {
.brw = 0x200000 ,
.cache = 0
},
.update = upload_drawing_rect
}
Definition at line 93 of file brw_misc_state.c.
Initial value:
{
.dirty = {
.brw = 0x200000 ,
.cache = 0
},
.update = upload_invarient_state
}
Definition at line 446 of file brw_misc_state.c.
Initial value:
{
.dirty = {
.brw = 0x40 ,
.cache = 0
},
.update = upload_line_stipple
}
Definition at line 327 of file brw_misc_state.c.
Initial value:
{
.dirty = {
.brw = 0x200000 ,
.cache = 0
},
.update = upload_pipe_control
}
Definition at line 359 of file brw_misc_state.c.
Initial value:
{
.dirty = {
.brw = 0,
.cache = ( (1<<BRW_VS_UNIT) |
(1<<BRW_GS_UNIT) |
(1<<BRW_GS_PROG) |
(1<<BRW_CLIP_UNIT) |
(1<<BRW_SF_UNIT) |
(1<<BRW_WM_UNIT) |
(1<<BRW_CC_UNIT) )
},
.update = upload_pipelined_state_pointers
}
Definition at line 170 of file brw_misc_state.c.
Initial value:
{
.dirty = {
.brw = 0x40 ,
.cache = 0
},
.update = upload_polygon_stipple
}
Definition at line 292 of file brw_misc_state.c.
| struct brw_tracked_state brw_psp_urb_cbs |
Initial value:
{
.dirty = {
.brw = 0x10000 ,
.cache = ( (1<<BRW_VS_UNIT) |
(1<<BRW_GS_UNIT) |
(1<<BRW_GS_PROG) |
(1<<BRW_CLIP_UNIT) |
(1<<BRW_SF_UNIT) |
(1<<BRW_WM_UNIT) |
(1<<BRW_CC_UNIT) )
},
.update = upload_psp_urb_cbs
}
Definition at line 192 of file brw_misc_state.c.
Initial value:
{
.dirty = {
.brw = 0x200000 ,
.cache = 0
},
.update = upload_state_base_address
}
Definition at line 482 of file brw_misc_state.c.
1.5.4