spu_main.h

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00001 /**************************************************************************
00002  * 
00003  * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
00004  * All Rights Reserved.
00005  * 
00006  * Permission is hereby granted, free of charge, to any person obtaining a
00007  * copy of this software and associated documentation files (the
00008  * "Software"), to deal in the Software without restriction, including
00009  * without limitation the rights to use, copy, modify, merge, publish,
00010  * distribute, sub license, and/or sell copies of the Software, and to
00011  * permit persons to whom the Software is furnished to do so, subject to
00012  * the following conditions:
00013  * 
00014  * The above copyright notice and this permission notice (including the
00015  * next paragraph) shall be included in all copies or substantial portions
00016  * of the Software.
00017  * 
00018  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00019  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00020  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
00021  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
00022  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
00023  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
00024  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
00025  * 
00026  **************************************************************************/
00027 
00028 #ifndef SPU_MAIN_H
00029 #define SPU_MAIN_H
00030 
00031 
00032 #include <spu_mfcio.h>
00033 
00034 #include "cell/common.h"
00035 #include "draw/draw_vertex.h"
00036 #include "pipe/p_state.h"
00037 
00038 
00039 
00040 #define MAX_WIDTH 1024
00041 #define MAX_HEIGHT 1024
00042 
00043 
00048 typedef union {
00049    ushort us[TILE_SIZE][TILE_SIZE];
00050    uint   ui[TILE_SIZE][TILE_SIZE];
00051    vector unsigned short us8[TILE_SIZE/2][TILE_SIZE/4];
00052    vector unsigned int ui4[TILE_SIZE/2][TILE_SIZE/2];
00053 } tile_t;
00054 
00055 
00056 #define TILE_STATUS_CLEAR   1
00057 #define TILE_STATUS_DEFINED 2  
00058 #define TILE_STATUS_CLEAN   3  
00059 #define TILE_STATUS_DIRTY   4  
00060 #define TILE_STATUS_GETTING 5  
00064 typedef vector float (*spu_sample_texture_func)(uint unit,
00065                                                 vector float texcoord);
00066 
00068 typedef void (*spu_fragment_ops_func)(uint x, uint y,
00069                                       tile_t *colorTile,
00070                                       tile_t *depthStencilTile,
00071                                       vector float fragZ,
00072                                       vector float fragRed,
00073                                       vector float fragGreen,
00074                                       vector float fragBlue,
00075                                       vector float fragAlpha,
00076                                       vector unsigned int mask);
00077 
00079 typedef void (*spu_fragment_program_func)(vector float *inputs,
00080                                           vector float *outputs,
00081                                           vector float *constants);
00082 
00083 
00084 struct spu_framebuffer
00085 {
00086    void *color_start;              
00087    void *depth_start;              
00088    enum pipe_format color_format;
00089    enum pipe_format depth_format;
00090    uint width, height;             
00091    uint width_tiles, height_tiles; 
00093    uint color_clear_value;
00094    uint depth_clear_value;
00095 
00096    uint zsize;                     
00097    float zscale;                   
00098 } ALIGN16_ATTRIB;
00099 
00100 
00101 struct spu_texture
00102 {
00103    void *start;
00104    ushort width, height;
00105    ushort tiles_per_row;
00106    vector float tex_size;
00107    vector unsigned int tex_size_mask; 
00108    vector unsigned int tex_size_x_mask; 
00109    vector unsigned int tex_size_y_mask; 
00110 } ALIGN16_ATTRIB;
00111 
00112 
00116 struct spu_global
00117 {
00119    struct cell_init_info init;
00120 
00121    /*
00122     * Current state
00123     */
00124    struct spu_framebuffer fb;
00125    struct pipe_depth_stencil_alpha_state depth_stencil_alpha;
00126    struct pipe_blend_state blend;
00127    struct pipe_sampler_state sampler[PIPE_MAX_SAMPLERS];
00128    struct spu_texture texture[PIPE_MAX_SAMPLERS];
00129    struct vertex_info vertex_info;
00130 
00132    tile_t ctile ALIGN16_ATTRIB;
00133    tile_t ztile ALIGN16_ATTRIB;
00134 
00136    boolean read_depth;
00137    boolean read_stencil;
00138 
00140    ubyte cur_ctile_status, cur_ztile_status;
00141 
00143    ubyte ctile_status[MAX_HEIGHT/TILE_SIZE][MAX_WIDTH/TILE_SIZE] ALIGN16_ATTRIB;
00144    ubyte ztile_status[MAX_HEIGHT/TILE_SIZE][MAX_WIDTH/TILE_SIZE] ALIGN16_ATTRIB;
00145 
00147    uint fragment_ops_code[SPU_MAX_FRAGMENT_OPS_INSTS];
00149    spu_fragment_ops_func fragment_ops;
00150 
00152    uint fragment_program_code[SPU_MAX_FRAGMENT_PROGRAM_INSTS];
00154    spu_fragment_program_func fragment_program;
00155 
00157    spu_sample_texture_func sample_texture[CELL_MAX_SAMPLERS];
00158 
00160 #define MAX_CONSTANTS 32
00161    vector float constants[MAX_CONSTANTS];
00162 
00163 } ALIGN16_ATTRIB;
00164 
00165 
00166 extern struct spu_global spu;
00167 extern boolean Debug;
00168 
00169 
00170 
00171 
00172 /* DMA TAGS */
00173 
00174 #define TAG_SURFACE_CLEAR     10
00175 #define TAG_VERTEX_BUFFER     11
00176 #define TAG_READ_TILE_COLOR   12
00177 #define TAG_READ_TILE_Z       13
00178 #define TAG_WRITE_TILE_COLOR  14
00179 #define TAG_WRITE_TILE_Z      15
00180 #define TAG_INDEX_BUFFER      16
00181 #define TAG_BATCH_BUFFER      17
00182 #define TAG_MISC              18
00183 #define TAG_DCACHE0           20
00184 #define TAG_DCACHE1           21
00185 #define TAG_DCACHE2           22
00186 #define TAG_DCACHE3           23
00187 
00188 
00189 
00190 static INLINE void
00191 wait_on_mask(unsigned tagMask)
00192 {
00193    mfc_write_tag_mask( tagMask );
00194    /* wait for completion of _any_ DMAs specified by tagMask */
00195    mfc_read_tag_status_any();
00196 }
00197 
00198 
00199 static INLINE void
00200 wait_on_mask_all(unsigned tagMask)
00201 {
00202    mfc_write_tag_mask( tagMask );
00203    /* wait for completion of _any_ DMAs specified by tagMask */
00204    mfc_read_tag_status_all();
00205 }
00206 
00207 
00208 
00209 
00210 
00211 static INLINE void
00212 memset16(ushort *d, ushort value, uint count)
00213 {
00214    uint i;
00215    for (i = 0; i < count; i++)
00216       d[i] = value;
00217 }
00218 
00219 
00220 static INLINE void
00221 memset32(uint *d, uint value, uint count)
00222 {
00223    uint i;
00224    for (i = 0; i < count; i++)
00225       d[i] = value;
00226 }
00227 
00228 
00229 #endif /* SPU_MAIN_H */

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