Display PLLs¶

Display PLLs used for driving outputs vary by platform. While some have per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL from a pool. In the latter scenario, it is possible that multiple pipes share a PLL if their configurations match.

This file provides an abstraction over display PLLs. The function intel_dpll_init() initializes the PLLs for the given platform. The users of a PLL are tracked and that tracking is integrated with the atomic modset interface. During an atomic operation, required PLLs can be reserved for a given CRTC and encoder configuration by calling intel_dpll_reserve() and previously reserved PLLs can be released with intel_dpll_release(). Changes to the users are first staged in the atomic state, and then made effective by calling intel_dpll_swap_state() during the atomic commit phase.

struct intel_dpll *intel_get_dpll_by_id(struct intel_display *display, enum intel_dpll_id id)¶: get a DPLL given its id

Parameters

struct intel_display *display: intel_display device instance
enum intel_dpll_id id: pll id

Return

A pointer to the DPLL with id

void intel_dpll_enable(const struct intel_crtc_state *crtc_state)¶: enable a CRTC’s DPLL

Parameters

const struct intel_crtc_state *crtc_state: CRTC, and its state, which has a DPLL

Description

Enable DPLL used by crtc.

void intel_dpll_disable(const struct intel_crtc_state *crtc_state)¶: disable a CRTC’s shared DPLL

Parameters

const struct intel_crtc_state *crtc_state: CRTC, and its state, which has a shared DPLL

Description

Disable DPLL used by crtc.

void intel_dpll_crtc_get(const struct intel_crtc *crtc, const struct intel_dpll *pll, struct intel_dpll_state *dpll_state)¶: Get a DPLL reference for a CRTC

Parameters

const struct intel_crtc *crtc: CRTC on which behalf the reference is taken
const struct intel_dpll *pll: DPLL for which the reference is taken
struct intel_dpll_state *dpll_state: the DPLL atomic state in which the reference is tracked

Description

Take a reference for pll tracking the use of it by crtc.

void intel_dpll_crtc_put(const struct intel_crtc *crtc, const struct intel_dpll *pll, struct intel_dpll_state *dpll_state)¶: Drop a DPLL reference for a CRTC

Parameters

const struct intel_crtc *crtc: CRTC on which behalf the reference is dropped
const struct intel_dpll *pll: DPLL for which the reference is dropped
struct intel_dpll_state *dpll_state: the DPLL atomic state in which the reference is tracked

Description

Drop a reference for pll tracking the end of use of it by crtc.

void intel_dpll_swap_state(struct intel_atomic_state *state)¶: make atomic DPLL configuration effective

Parameters

struct intel_atomic_state *state: atomic state

Description

This is the dpll version of drm_atomic_helper_swap_state() since the helper does not handle driver-specific global state.

For consistency with atomic helpers this function does a complete swap, i.e. it also puts the current state into state, even though there is no need for that at this moment.

void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, enum icl_port_dpll_id port_dpll_id)¶: select the active port DPLL for a given CRTC

Parameters

struct intel_crtc_state *crtc_state: state for the CRTC to select the DPLL for
enum icl_port_dpll_id port_dpll_id: the active port_dpll_id to select

Description

Select the given port_dpll_id instance from the DPLLs reserved for the CRTC.

void intel_dpll_init(struct intel_display *display)¶: Initialize DPLLs

Parameters

struct intel_display *display: intel_display device

Description

Initialize DPLLs for display.

int intel_dpll_compute(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)¶: compute DPLL state CRTC and encoder combination

Parameters

struct intel_atomic_state *state: atomic state
struct intel_crtc *crtc: CRTC to compute DPLLs for
struct intel_encoder *encoder: encoder

Description

This function computes the DPLL state for the given CRTC and encoder.

The new configuration in the atomic commit state is made effective by calling intel_dpll_swap_state().

Return

0 on success, negative error code on failure.

int intel_dpll_reserve(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)¶: reserve DPLLs for CRTC and encoder combination

Parameters

struct intel_atomic_state *state: atomic state
struct intel_crtc *crtc: CRTC to reserve DPLLs for
struct intel_encoder *encoder: encoder

Description

This function reserves all required DPLLs for the given CRTC and encoder combination in the current atomic commit state and the new crtc atomic state.

The new configuration in the atomic commit state is made effective by calling intel_dpll_swap_state().

The reserved DPLLs should be released by calling intel_dpll_release().

Return

0 if all required DPLLs were successfully reserved, negative error code otherwise.

void intel_dpll_release(struct intel_atomic_state *state, struct intel_crtc *crtc)¶: end use of DPLLs by CRTC in atomic state

Parameters

struct intel_atomic_state *state: atomic state
struct intel_crtc *crtc: crtc from which the DPLLs are to be released

Description

This function releases all DPLLs reserved by intel_dpll_reserve() from the current atomic commit state and the old crtc atomic state.

The new configuration in the atomic commit state is made effective by calling intel_dpll_swap_state().

void intel_dpll_update_active(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder)¶: update the active DPLL for a CRTC/encoder

Parameters

struct intel_atomic_state *state: atomic state
struct intel_crtc *crtc: the CRTC for which to update the active DPLL
struct intel_encoder *encoder: encoder determining the type of port DPLL

Description

Update the active DPLL for the given crtc/encoder in crtc’s atomic state, from the port DPLLs reserved previously by intel_dpll_reserve(). The DPLL selected will be based on the current mode of the encoder’s port.

int intel_dpll_get_freq(struct intel_display *display, const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state)¶: calculate the DPLL’s output frequency

Parameters

struct intel_display *display: intel_display device
const struct intel_dpll *pll: DPLL for which to calculate the output frequency
const struct intel_dpll_hw_state *dpll_hw_state: DPLL state from which to calculate the output frequency

Description

Return the output frequency corresponding to pll’s passed in dpll_hw_state.

bool intel_dpll_get_hw_state(struct intel_display *display, struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state)¶: readout the DPLL’s hardware state

Parameters

struct intel_display *display: intel_display device instance
struct intel_dpll *pll: DPLL for which to calculate the output frequency
struct intel_dpll_hw_state *dpll_hw_state: DPLL’s hardware state

Description

Read out pll’s hardware state into dpll_hw_state.

void intel_dpll_dump_hw_state(struct intel_display *display, struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state)¶: dump hw_state

Parameters

struct intel_display *display: intel_display structure
struct drm_printer *p: where to print the state to
const struct intel_dpll_hw_state *dpll_hw_state: hw state to be dumped

Description

Dumo out the relevant values in dpll_hw_state.

bool intel_dpll_compare_hw_state(struct intel_display *display, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b)¶: compare the two states

Parameters

struct intel_display *display: intel_display structure
const struct intel_dpll_hw_state *a: first DPLL hw state
const struct intel_dpll_hw_state *b: second DPLL hw state

Description

Compare DPLL hw states a and b.

Return

true if the states are equal, false if the differ

enum intel_dpll_id¶: possible DPLL ids

Constants

DPLL_ID_PRIVATE

non-shared dpll in use

DPLL_ID_PCH_PLL_A

DPLL A in ILK, SNB and IVB

DPLL_ID_PCH_PLL_B

DPLL B in ILK, SNB and IVB

DPLL_ID_WRPLL1

HSW and BDW WRPLL1

DPLL_ID_WRPLL2

HSW and BDW WRPLL2

DPLL_ID_SPLL

HSW and BDW SPLL

DPLL_ID_LCPLL_810

HSW and BDW 0.81 GHz LCPLL

DPLL_ID_LCPLL_1350

HSW and BDW 1.35 GHz LCPLL

DPLL_ID_LCPLL_2700

HSW and BDW 2.7 GHz LCPLL

DPLL_ID_SKL_DPLL0

SKL and later DPLL0

DPLL_ID_SKL_DPLL1

SKL and later DPLL1

DPLL_ID_SKL_DPLL2

SKL and later DPLL2

DPLL_ID_SKL_DPLL3

SKL and later DPLL3

DPLL_ID_ICL_DPLL0

ICL/TGL combo PHY DPLL0

DPLL_ID_ICL_DPLL1

ICL/TGL combo PHY DPLL1

DPLL_ID_EHL_DPLL4

EHL combo PHY DPLL4

DPLL_ID_ICL_TBTPLL

ICL/TGL TBT PLL

DPLL_ID_ICL_MGPLL1

ICL MG PLL 1 port 1 (C),: TGL TC PLL 1 port 1 (TC1)

DPLL_ID_ICL_MGPLL2

ICL MG PLL 1 port 2 (D): TGL TC PLL 1 port 2 (TC2)

DPLL_ID_ICL_MGPLL3

ICL MG PLL 1 port 3 (E): TGL TC PLL 1 port 3 (TC3)

DPLL_ID_ICL_MGPLL4

ICL MG PLL 1 port 4 (F): TGL TC PLL 1 port 4 (TC4)

DPLL_ID_TGL_MGPLL5

TGL TC PLL port 5 (TC5)

DPLL_ID_TGL_MGPLL6

TGL TC PLL port 6 (TC6)

DPLL_ID_DG1_DPLL0

DG1 combo PHY DPLL0

DPLL_ID_DG1_DPLL1

DG1 combo PHY DPLL1

DPLL_ID_DG1_DPLL2

DG1 combo PHY DPLL2

DPLL_ID_DG1_DPLL3

DG1 combo PHY DPLL3

Description

Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.

struct intel_dpll_state¶: hold the DPLL atomic state

Definition:

struct intel_dpll_state {
    u8 pipe_mask;
    struct intel_dpll_hw_state hw_state;
};

Members

pipe_mask: mask of pipes using this DPLL, active or not
hw_state: hardware configuration for the DPLL stored in struct intel_dpll_hw_state.

Description

This structure holds an atomic state for the DPLL, that can represent either its current state (in struct intel_shared_dpll) or a desired future state which would be applied by an atomic mode set (stored in a struct intel_atomic_state).

See also intel_reserve_shared_dplls() and intel_release_shared_dplls().

struct dpll_info¶: display PLL platform specific info

Definition:

struct dpll_info {
    const char *name;
    const struct intel_dpll_funcs *funcs;
    enum intel_dpll_id id;
    enum intel_display_power_domain power_domain;
    bool always_on;
    bool is_alt_port_dpll;
};

Members

name: DPLL name; used for logging
funcs: platform specific hooks
id: unique identifier for this DPLL
power_domain: extra power domain required by the DPLL
always_on: Inform the state checker that the DPLL is kept enabled even if not in use by any CRTC.
is_alt_port_dpll: Inform the state checker that the DPLL can be used as a fallback (for TC->TBT fallback).

struct intel_dpll¶: display PLL with tracked state and users

Definition:

struct intel_dpll {
    struct intel_dpll_state state;
    u8 index;
    u8 active_mask;
    bool on;
    const struct dpll_info *info;
    struct ref_tracker *wakeref;
};

Members

state: Store the state for the pll, including its hw state and CRTCs using it.
index: index for atomic state
active_mask: mask of active pipes (i.e. DPMS on) using this DPLL
on: is the PLL actually active? Disabled during modeset
info: platform specific info
wakeref: In some platforms a device-level runtime pm reference may need to be grabbed to disable DC states while this DPLL is enabled