Display FIFO Underrun Reporting¶
The i915 driver checks for display fifo underruns using the interrupt signals provided by the hardware. This is enabled by default and fairly useful to debug display issues, especially watermark settings.
If an underrun is detected this is logged into dmesg. To avoid flooding logs and occupying the cpu underrun interrupts are disabled after the first occurrence until the next modeset on a given pipe.
Note that underrun detection on gmch platforms is a bit more ugly since there is no interrupt (despite that the signalling bit is in the PIPESTAT pipe interrupt register). Also on some other platforms underrun interrupts are shared, which means that if we detect an underrun we need to disable underrun reporting on all pipes.
The code also supports underrun detection on the PCH transcoder.
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bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable)¶
set cpu fifo underrun reporting state
Parameters
struct intel_display *displaydisplay device instance
enum pipe pipe(CPU) pipe to set state for
bool enablewhether underruns should be reported or not
Description
This function sets the fifo underrun state for pipe. It is used in the modeset code to avoid false positives since on many platforms underruns are expected when disabling or enabling the pipe.
Notice that on some platforms disabling underrun reports for one pipe disables for all due to shared interrupts. Actual reporting is still per-pipe though.
Returns the previous state of underrun reporting.
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bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display, enum pipe pch_transcoder, bool enable)¶
set PCH fifo underrun reporting state
Parameters
struct intel_display *displaydisplay device instance
enum pipe pch_transcoderthe PCH transcoder (same as pipe on IVB and older)
bool enablewhether underruns should be reported or not
Description
This function makes us disable or enable PCH fifo underruns for a specific PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO underrun reporting for one transcoder may also disable all the other PCH error interruts for the other transcoders, due to the fact that there’s just one interrupt mask/enable bit for all the transcoders.
Returns the previous state of underrun reporting.
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void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display, enum pipe pipe)¶
handle CPU fifo underrun interrupt
Parameters
struct intel_display *displaydisplay device instance
enum pipe pipe(CPU) pipe to set state for
Description
This handles a CPU fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.
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void intel_pch_fifo_underrun_irq_handler(struct intel_display *display, enum pipe pch_transcoder)¶
handle PCH fifo underrun interrupt
Parameters
struct intel_display *displaydisplay device instance
enum pipe pch_transcoderthe PCH transcoder (same as pipe on IVB and older)
Description
This handles a PCH fifo underrun interrupt, generating an underrun warning into dmesg if underrun reporting is enabled and then disables the underrun interrupt to avoid an irq storm.
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void intel_check_cpu_fifo_underruns(struct intel_display *display)¶
check for CPU fifo underruns immediately
Parameters
struct intel_display *displaydisplay device instance
Description
Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared error interrupt may have been disabled, and so CPU fifo underruns won’t necessarily raise an interrupt, and on GMCH platforms where underruns never raise an interrupt.
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void intel_check_pch_fifo_underruns(struct intel_display *display)¶
check for PCH fifo underruns immediately
Parameters
struct intel_display *displaydisplay device instance
Description
Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared error interrupt may have been disabled, and so PCH fifo underruns won’t necessarily raise an interrupt.