cell_gen_fp.c File Reference

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Data Structures
struct	codegen
	Context needed during code generation. More...
Defines
#define	DISASSEM   01
	Generate SPU fragment program/shader code.
Functions
static int	get_itemp (struct codegen *gen)
	Allocate an intermediate temporary register.
static void	free_itemps (struct codegen *gen)
	Free all intermediate temporary registers.
static int	get_const_one_reg (struct codegen *gen)
	Return index of an SPE register containing {1.0, 1.0, 1.0, 1.0}.
static int	get_src_reg (struct codegen *gen, int channel, const struct tgsi_full_src_register *src)
	Return the index of the SPU temporary containing the named TGSI source register.
static int	get_dst_reg (struct codegen *gen, int channel, const struct tgsi_full_dst_register *dest)
	Return the index of an SPE register to use for the given TGSI register.
static void	store_dest_reg (struct codegen *gen, int value_reg, int channel, const struct tgsi_full_dst_register *dest)
	When a TGSI instruction is writing to an output register, this function emits the SPE store instruction to store the value_reg.
static boolean	emit_MOV (struct codegen *gen, const struct tgsi_full_instruction *inst)
static boolean	emit_ADD (struct codegen *gen, const struct tgsi_full_instruction *inst)
	Emit addition instructions.
static boolean	emit_MUL (struct codegen *gen, const struct tgsi_full_instruction *inst)
	Emit multiply.
static boolean	emit_SGT (struct codegen *gen, const struct tgsi_full_instruction *inst)
	Emit set-if-greater-than.
static boolean	emit_END (struct codegen *gen)
	Emit END instruction.
static boolean	emit_instruction (struct codegen *gen, const struct tgsi_full_instruction *inst)
	Emit code for the given instruction.
static void	emit_declaration (struct codegen *gen, const struct tgsi_full_declaration *decl)
	Emit "code" for a TGSI declaration.
boolean	cell_gen_fragment_program (struct cell_context *cell, const struct tgsi_token *tokens, struct spe_function *f)
	Translate TGSI shader code to SPE instructions.

---

Define Documentation

#define DISASSEM   01

Generate SPU fragment program/shader code.

Note that we generate SOA-style code here. So each TGSI instruction operates on four pixels (and is translated into four SPU instructions, generally speaking).

Author:

Brian Paul Set to 1 to enable debug/disassembly printfs

Definition at line 55 of file cell_gen_fp.c.

---

Function Documentation

boolean cell_gen_fragment_program	(	struct cell_context *	cell,
		const struct tgsi_token *	tokens,
		struct spe_function *	f
	)

Translate TGSI shader code to SPE instructions.

This is done when the state tracker gives us a new shader (via pipe->create_fs_state()).

Parameters:

	cell	the rendering context (in)
	tokens	the TGSI shader (in)
	f	the generated function (out)

Definition at line 455 of file cell_gen_fp.c.

References assert, codegen::constants_reg, emit_declaration(), emit_END(), emit_instruction(), codegen::error, codegen::f, tgsi_full_token::FullDeclaration, tgsi_full_token::FullImmediate, tgsi_full_token::FullInstruction, tgsi_parse_context::FullToken, codegen::inputs_reg, spe_function::num_inst, codegen::outputs_reg, spe_allocate_register(), spe_init_func(), SPE_INST_SIZE, SPU_MAX_FRAGMENT_PROGRAM_INSTS, tgsi_dump(), tgsi_parse_end_of_tokens(), tgsi_parse_free(), tgsi_parse_init(), tgsi_parse_token(), TGSI_TOKEN_TYPE_DECLARATION, TGSI_TOKEN_TYPE_IMMEDIATE, TGSI_TOKEN_TYPE_INSTRUCTION, tgsi_full_token::Token, and tgsi_token::Type.

{
   struct tgsi_parse_context parse;
   struct codegen gen;

   memset(&gen, 0, sizeof(gen));
   gen.f = f;

   /* For SPE function calls: reg $3 = first param, $4 = second param, etc. */
   gen.inputs_reg = 3;     /* pointer to inputs array */
   gen.outputs_reg = 4;    /* pointer to outputs array */
   gen.constants_reg = 5;  /* pointer to constants array */

   spe_init_func(f, SPU_MAX_FRAGMENT_PROGRAM_INSTS * SPE_INST_SIZE);
   spe_allocate_register(f, gen.inputs_reg);
   spe_allocate_register(f, gen.outputs_reg);
   spe_allocate_register(f, gen.constants_reg);

#if DISASSEM
   printf("Begin %s\n", __FUNCTION__);
   tgsi_dump(tokens, 0);
#endif

   tgsi_parse_init(&parse, tokens);

   while (!tgsi_parse_end_of_tokens(&parse) && !gen.error) {
      tgsi_parse_token(&parse);

      switch (parse.FullToken.Token.Type) {
      case TGSI_TOKEN_TYPE_IMMEDIATE:
#if 0
         if (!note_immediate(&gen, &parse.FullToken.FullImmediate ))
            goto fail;
#endif
         break;

      case TGSI_TOKEN_TYPE_DECLARATION:
         emit_declaration(&gen, &parse.FullToken.FullDeclaration);
         break;

      case TGSI_TOKEN_TYPE_INSTRUCTION:
         if (!emit_instruction(&gen, &parse.FullToken.FullInstruction )) {
            gen.error = true;
         }
         break;

      default:
         assert(0);

      }
   }


   if (gen.error) {
      /* terminate the SPE code */
      return emit_END(&gen);
   }

#if DISASSEM
   printf("cell_gen_fragment_program nr instructions: %d\n", f->num_inst);
   printf("End %s\n", __FUNCTION__);
#endif

   tgsi_parse_free( &parse );

   return !gen.error;
}

static boolean emit_ADD	(	struct codegen *	gen,
		const struct tgsi_full_instruction *	inst
	)			[static]

Emit addition instructions.

Recall that a single TGSI_OPCODE_ADD becomes (up to) four SPU "fa" instructions because we're doing SOA processing.

Definition at line 262 of file cell_gen_fp.c.

References tgsi_full_dst_register::DstRegister, codegen::f, free_itemps(), tgsi_full_instruction::FullDstRegisters, tgsi_full_instruction::FullSrcRegisters, get_dst_reg(), get_src_reg(), spe_fa(), store_dest_reg(), and tgsi_dst_register::WriteMask.

{
   int ch;
   /* Loop over Red/Green/Blue/Alpha channels */
   for (ch = 0; ch < 4; ch++) {
      /* If the dest R, G, B or A writemask is enabled... */
      if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
         /* get indexes of the two src, one dest SPE registers */
         int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
         int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
         int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);

         /* Emit actual SPE instruction: d = s1 + s2 */
         spe_fa(gen->f, d_reg, s1_reg, s2_reg);
#if DISASSEM
         printf("fa\tr%d, r%d, r%d\n", d_reg, s1_reg, s2_reg);
#endif

         /* Store the result (a no-op for TGSI_FILE_TEMPORARY dests) */
         store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
         /* Free any intermediate temps we allocated */
         free_itemps(gen);
      }
   }
   return true;
}

static void emit_declaration	(	struct codegen *	gen,
		const struct tgsi_full_declaration *	decl
	)			[static]

Emit "code" for a TGSI declaration.

We only care about TGSI TEMPORARY register declarations at this time. For each TGSI TEMPORARY we allocate four SPE registers.

Definition at line 409 of file cell_gen_fp.c.

References tgsi_full_declaration::Declaration, tgsi_full_declaration::DeclarationRange, codegen::f, tgsi_declaration::File, tgsi_declaration_range::First, tgsi_declaration_range::Last, spe_allocate_available_register(), codegen::temp_regs, and TGSI_FILE_TEMPORARY.

{
   int i, ch;

   switch (decl->Declaration.File) {
   case TGSI_FILE_TEMPORARY:
#if DISASSEM
      printf("Declare temp reg %d .. %d\n",
             decl->DeclarationRange.First,
             decl->DeclarationRange.Last);
#endif
      for (i = decl->DeclarationRange.First;
           i <= decl->DeclarationRange.Last;
           i++) {
         for (ch = 0; ch < 4; ch++) {
            gen->temp_regs[i][ch] = spe_allocate_available_register(gen->f);
         }

         /* XXX if we run out of SPE registers, we need to spill
          * to SPU memory.  someday...
          */

#if DISASSEM
         printf("  SPE regs: %d %d %d %d\n",
                gen->temp_regs[i][0],
                gen->temp_regs[i][1],
                gen->temp_regs[i][2],
                gen->temp_regs[i][3]);
#endif
      }
      break;
   default:
      ; /* ignore */
   }
}

static boolean emit_END

(

struct codegen *

gen

)

[static]

Emit END instruction.

We just return from the shader function at this point.

Note that there may be more code after this that would be called by TGSI_OPCODE_CALL.

Definition at line 362 of file cell_gen_fp.c.

References codegen::f, spe_bi(), and SPE_REG_RA.

{
   /* return from function call */
   spe_bi(gen->f, SPE_REG_RA, 0, 0);
#if DISASSEM
   printf("bi\trRA\n");
#endif
   return true;
}

static boolean emit_instruction	(	struct codegen *	gen,
		const struct tgsi_full_instruction *	inst
	)			[static]

Emit code for the given instruction.

Just a big switch stmt.

Definition at line 377 of file cell_gen_fp.c.

References emit_ADD(), emit_END(), emit_MOV(), emit_MUL(), emit_SGT(), tgsi_full_instruction::Instruction, tgsi_instruction::Opcode, TGSI_OPCODE_ADD, TGSI_OPCODE_END, TGSI_OPCODE_MOV, TGSI_OPCODE_MUL, and TGSI_OPCODE_SGT.

{
   switch (inst->Instruction.Opcode) {
   case TGSI_OPCODE_MOV:
      return emit_MOV(gen, inst);
   case TGSI_OPCODE_MUL:
      return emit_MUL(gen, inst);
   case TGSI_OPCODE_ADD:
      return emit_ADD(gen, inst);
   case TGSI_OPCODE_SGT:
      return emit_SGT(gen, inst);
   case TGSI_OPCODE_END:
      return emit_END(gen);

   /* XXX lots more cases to do... */

   default:
      return false;
   }

   return true;
}

static boolean emit_MOV	(	struct codegen *	gen,
		const struct tgsi_full_instruction *	inst
	)			[static]

Definition at line 236 of file cell_gen_fp.c.

References tgsi_full_dst_register::DstRegister, codegen::f, free_itemps(), tgsi_full_instruction::FullDstRegisters, tgsi_full_instruction::FullSrcRegisters, get_dst_reg(), get_src_reg(), spe_move(), store_dest_reg(), and tgsi_dst_register::WriteMask.

{
   int ch;
   for (ch = 0; ch < 4; ch++) {
      if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
         int src_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
         int dst_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
         /* XXX we don't always need to actually emit a mov instruction here */
         spe_move(gen->f, dst_reg, src_reg);
#if DISASSEM
         printf("mov\tr%d, r%d\n", dst_reg, src_reg);
#endif
         store_dest_reg(gen, dst_reg, ch, &inst->FullDstRegisters[0]);
         free_itemps(gen);
      }
   }
   return true;
}

static boolean emit_MUL	(	struct codegen *	gen,
		const struct tgsi_full_instruction *	inst
	)			[static]

Emit multiply.

See emit_ADD for comments.

Definition at line 294 of file cell_gen_fp.c.

References tgsi_full_dst_register::DstRegister, codegen::f, free_itemps(), tgsi_full_instruction::FullDstRegisters, tgsi_full_instruction::FullSrcRegisters, get_dst_reg(), get_src_reg(), spe_fm(), store_dest_reg(), and tgsi_dst_register::WriteMask.

{
   int ch;
   for (ch = 0; ch < 4; ch++) {
      if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
         int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
         int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
         int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
         /* d = s1 * s2 */
         spe_fm(gen->f, d_reg, s1_reg, s2_reg);
#if DISASSEM
         printf("fm\tr%d, r%d, r%d\n", d_reg, s1_reg, s2_reg);
#endif
         store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
         free_itemps(gen);
      }
   }
   return true;
}

static boolean emit_SGT	(	struct codegen *	gen,
		const struct tgsi_full_instruction *	inst
	)			[static]

Emit set-if-greater-than.

Note that the SPE fcgt instruction produces 0x0 and 0xffffffff as the result but OpenGL/TGSI needs 0.0 and 1.0 results. We can easily convert 0x0/0xffffffff to 0.0/1.0 with a bitwise AND.

Definition at line 322 of file cell_gen_fp.c.

References tgsi_full_dst_register::DstRegister, codegen::f, free_itemps(), tgsi_full_instruction::FullDstRegisters, tgsi_full_instruction::FullSrcRegisters, get_const_one_reg(), get_dst_reg(), get_src_reg(), spe_and(), spe_fcgt(), store_dest_reg(), and tgsi_dst_register::WriteMask.

{
   int ch;

   for (ch = 0; ch < 4; ch++) {
      if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
         int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
         int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
         int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);

         /* d = (s1 > s2) */
         spe_fcgt(gen->f, d_reg, s1_reg, s2_reg);
#if DISASSEM
         printf("fcgt\tr%d, r%d, r%d\n", d_reg, s1_reg, s2_reg);
#endif

         /* convert d from 0x0/0xffffffff to 0.0/1.0 */
         /* d = d & one_reg */
         spe_and(gen->f, d_reg, d_reg, get_const_one_reg(gen));
#if DISASSEM
         printf("and\tr%d, r%d, r%d\n", d_reg, d_reg, get_const_one_reg(gen));
#endif

         store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
         free_itemps(gen);
      }
   }

   return true;
}

static void free_itemps

(

struct codegen *

gen

)

[static]

Free all intermediate temporary registers.

To be called after each instruction has been emitted.

Definition at line 96 of file cell_gen_fp.c.

References codegen::f, codegen::itemps, codegen::num_itemps, and spe_release_register().

{
   int i;
   for (i = 0; i < gen->num_itemps; i++) {
      spe_release_register(gen->f, gen->itemps[i]);
   }
   gen->num_itemps = 0;
}

static int get_const_one_reg

(

struct codegen *

gen

)

[static]

Return index of an SPE register containing {1.0, 1.0, 1.0, 1.0}.

The register is allocated and initialized upon the first call.

Definition at line 111 of file cell_gen_fp.c.

References codegen::f, codegen::one_reg, spe_allocate_available_register(), and spe_load_float().

{
   if (gen->one_reg <= 0) {
      gen->one_reg = spe_allocate_available_register(gen->f);
   }

   /* one = {1.0, 1.0, 1.0, 1.0} */
   spe_load_float(gen->f, gen->one_reg, 1.0f);
#if DISASSEM
   printf("il\tr%d, 1.0f\n", gen->one_reg);
#endif

   return gen->one_reg;
}

static int get_dst_reg	(	struct codegen *	gen,
		int	channel,
		const struct tgsi_full_dst_register *	dest
	)			[static]

Return the index of an SPE register to use for the given TGSI register.

If the TGSI register is TGSI_FILE_TEMPORARAY, the index of the corresponding SPE register is returned. If the TGSI register is TGSI_FILE_OUTPUT we allocate an intermediate temporary register. See store_dest_reg() below...

Definition at line 182 of file cell_gen_fp.c.

References assert, tgsi_full_dst_register::DstRegister, tgsi_dst_register::File, get_itemp(), tgsi_dst_register::Index, codegen::temp_regs, TGSI_FILE_OUTPUT, and TGSI_FILE_TEMPORARY.

{
   int reg;

   switch (dest->DstRegister.File) {
   case TGSI_FILE_TEMPORARY:
      reg = gen->temp_regs[dest->DstRegister.Index][channel];
      break;
   case TGSI_FILE_OUTPUT:
      reg = get_itemp(gen);
      break;
   default:
      assert(0);
   }

   return reg;
}

static int get_itemp

(

struct codegen *

gen

)

[static]

Allocate an intermediate temporary register.

Definition at line 83 of file cell_gen_fp.c.

References assert, Elements, codegen::f, codegen::itemps, codegen::num_itemps, and spe_allocate_available_register().

{
   int t = spe_allocate_available_register(gen->f);
   assert(gen->num_itemps < Elements(gen->itemps));
   gen->itemps[gen->num_itemps++] = t;
   return t;
}

static int get_src_reg	(	struct codegen *	gen,
		int	channel,
		const struct tgsi_full_src_register *	src
	)			[static]

Return the index of the SPU temporary containing the named TGSI source register.

If the TGSI register is a TGSI_FILE_TEMPORARY we just return the corresponding SPE register. If the TGIS register is TGSI_FILE_INPUT/CONSTANT/IMMEDIATE we allocate a new SPE register and emit an SPE load instruction.

Definition at line 135 of file cell_gen_fp.c.

References assert, codegen::f, tgsi_src_register::File, get_itemp(), tgsi_src_register::Index, codegen::inputs_reg, offset(), spe_lqd(), tgsi_full_src_register::SrcRegister, codegen::temp_regs, TGSI_FILE_CONSTANT, TGSI_FILE_IMMEDIATE, TGSI_FILE_INPUT, and TGSI_FILE_TEMPORARY.

{
   int reg;

   /* XXX need to examine src swizzle info here.
    * That will involve changing the channel var...
    */


   switch (src->SrcRegister.File) {
   case TGSI_FILE_TEMPORARY:
      reg = gen->temp_regs[src->SrcRegister.Index][channel];
      break;
   case TGSI_FILE_INPUT:
      {
         /* offset is measured in quadwords, not bytes */
         int offset = src->SrcRegister.Index * 4 + channel;
         reg = get_itemp(gen);
         /* Load:  reg = memory[(machine_reg) + offset] */
         spe_lqd(gen->f, reg, gen->inputs_reg, offset);
#if DISASSEM
         printf("lqd\tr%d, r%d + %d\n", reg, gen->inputs_reg, offset);
#endif
      }
      break;
   case TGSI_FILE_IMMEDIATE:
      /* xxx fall-through for now / fix */
   case TGSI_FILE_CONSTANT:
      /* xxx fall-through for now / fix */
   default:
      assert(0);
   }

   return reg;
}

static void store_dest_reg	(	struct codegen *	gen,
		int	value_reg,
		int	channel,
		const struct tgsi_full_dst_register *	dest
	)			[static]

When a TGSI instruction is writing to an output register, this function emits the SPE store instruction to store the value_reg.

Parameters:

value_reg

the SPE register containing the value to store. This would have been returned by get_dst_reg().

Definition at line 210 of file cell_gen_fp.c.

References assert, tgsi_full_dst_register::DstRegister, codegen::f, tgsi_dst_register::File, tgsi_dst_register::Index, offset(), codegen::outputs_reg, spe_stqd(), TGSI_FILE_OUTPUT, and TGSI_FILE_TEMPORARY.

{
   switch (dest->DstRegister.File) {
   case TGSI_FILE_TEMPORARY:
      /* no-op */
      break;
   case TGSI_FILE_OUTPUT:
      {
         /* offset is measured in quadwords, not bytes */
         int offset = dest->DstRegister.Index * 4 + channel;
         /* Store: memory[(machine_reg) + offset] = reg */
         spe_stqd(gen->f, value_reg, gen->outputs_reg, offset);
#if DISASSEM
         printf("stqd\tr%d, r%d + %d\n", value_reg, gen->outputs_reg, offset);
#endif
      }
      break;
   default:
      assert(0);
   }
}

---