- v -

• v : prim_header , ureg_program , float4
• valid : brw_constant_buffer , brw_vertex_element_state
• validate : draw_context , _DriBufferPool
• validMask : _DriSlabPool
• value : drmI830SetParam , _OverlayInfo , cso_node , tgsi_any_token , util_cache_entry , hash_table_item , cell_command_clear_surface , debug_named_value , drmI830GetParam
• value_mask : pipe_stencil_state
• varient : draw_vertex_shader
• varray : draw_context
• varying : brw_vertex_info
• vb : brw_context , brw_array_state , brw_vb_array_state
• vb0 : brw_array_state , brw_vertex_buffer_state
• vb_index : brw_array_state , brw_vertex_buffer_state
• vbo : i915_context , i915_vbuf_render
• vbo_alloc_size : i915_vbuf_render
• vbo_array : brw_context
• vbo_flushed : i915_context
• vbo_offset : i915_context , i915_vbuf_render
• vbo_ptr : i915_vbuf_render
• vbo_size : i915_vbuf_render
• vbuf : blit_state , gen_mipmap_state , cell_context , softpipe_context , st_context
• vbuf_render : cell_context , softpipe_context
• vbuf_slot : blit_state , gen_mipmap_state , st_context
• vbuffer : draw_context
• vcache : draw_context
• ve : brw_vertex_element_packet
• ve0 : brw_vertex_element_state
• ve1 : brw_vertex_element_state
• vendor : st_context
• Version : tgsi_full_version
• version : tgsi_iterate_context , tgsi_any_token , egl_drm_device
• vert : brw_sf_compile
• vert_cache_disable : brw_vs_unit_state
• vert_line_stride : brw_surface_state
• vert_line_stride_ofs : brw_surface_state
• vert_shader : gen_mipmap_state , st_context , blit_state
• vert_shaders : st_context
• vertex : brw_clip_compile , brw_gs_compile
• vertex_buf : cell_command_render , cell_command_release_verts , cell_vbuf_render
• vertex_buffer : draw_context , cell_context , cell_vbuf_render , i915_context , softpipe_context , softpipe_vbuf_render
• vertex_buffer_index : brw_vertex_element_state , pipe_vertex_element
• vertex_buffers : failover_context , st_context
• vertex_count : draw_context
• vertex_data_offset : fetch_pipeline_middle_end
• vertex_element : draw_context , cell_context , softpipe_context
• vertex_elements : failover_context , st_context
• vertex_fetch : spu_vs_context
• vertex_id : vertex_header
• vertex_info : cell_context , spu_global , i915_state , softpipe_context
• vertex_info_vbuf : softpipe_context
• vertex_position_space : brw_clip_unit_state
• vertex_programs : st_fragment_program
• vertex_ptr : vbuf_stage
• vertex_result_to_slot : st_context
• vertex_shader : cso_context , draw_context , failover_context
• vertex_shader_saved : cso_context
• vertex_size : cell_command_render , vbuf_stage , pt_fetch , fetch_pipeline_middle_end , cell_vbuf_render , i915_vbuf_render , softpipe_vbuf_render
• vertex_stride : draw_context
• vertexPool : intel_be_device
• VertexProgram : brw_context
• vertices : vbuf_stage , blit_state , gen_mipmap_state , st_context
• verts : draw_context
• verts_per_instance : brw_3d_primitive
• vf_fence : brw_urb_fence
• vfcomponent0 : brw_vertex_element_state
• vfcomponent1 : brw_vertex_element_state
• vfcomponent2 : brw_vertex_element_state
• vfcomponent3 : brw_vertex_element_state
• vfe_realloc : brw_urb_fence
• viewport : softpipe_context , blit_state , gen_mipmap_state , cell_context , failover_context , i915_context , brw_sf_viewport , st_context , spu_vs_context , draw_vs_varient_key
• Viewport : brw_context
• viewport : draw_context
• viewport_transform : brw_sf_unit_state
• viewport_xmax : brw_clip_unit_state
• viewport_xmin : brw_clip_unit_state
• viewport_xy_clip_enable : brw_clip_unit_state
• viewport_ymax : brw_clip_unit_state
• viewport_ymin : brw_clip_unit_state
• viewport_z_clip_enable : brw_clip_unit_state
• vinfo : vbuf_stage , fetch_shade_emit , fetch_emit_middle_end , pt_emit
• virtual : pb_slab , _DriKernelBO
• virtualX : drmI830Sarea
• virtualY : drmI830Sarea
• vishandle : xmesa_visual
• visinfo : xmesa_visual
• VisInfo : xlib_egl_surface
• vmax : setup_stage , setup_context
• vmid : setup_stage , setup_context
• vmin : setup_stage , setup_context
• vOut : cell_command_vs
• vp : st_context , translated_vertex_program , brw_vs_compile
• vp_gs_offset : brw_context
• vp_output : pipe_setup_linkage
• vp_output_count : brw_sf_prog_key
• vp_saved : cso_context
• vprovoke : setup_stage , setup_context
• vs : st_context , blit_state , brw_pipelined_state_pointers , gen_mipmap_state , st_context , cell_context , brw_binding_table_pointers , brw_context , draw_vs_varient , softpipe_context , draw_context , st_context , cell_command
• vs5 : brw_vs_unit_state
• vs6 : brw_vs_unit_state
• vs_enable : brw_vs_unit_state
• vs_fence : brw_urb_fence
• vs_hash : cso_cache
• vs_output : draw_varient_output
• vs_realloc : brw_urb_fence
• vs_size : brw_context
• vs_start : brw_context
• vsize : brw_context
• vstride : brw_reg
• vtbl : pb_buffer

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