- s -

• s_wrap_mode : brw_sampler_state
• sample_texture : spu_global
• sampler : ureg_program , spu_global , st_context , failover_context , blit_state , i915_state , i915_context , aaline_stage , gen_mipmap_state , brw_context , brw_instruction , cell_context , brw_instruction , softpipe_context
• sampler_count : brw_context , brw_gs_unit_state , brw_vs_unit_state , brw_wm_unit_state
• sampler_cso : aaline_stage , pstip_stage
• sampler_enable_flags : i915_state
• sampler_enable_nr : i915_state
• sampler_gs_offset : brw_context
• sampler_hash : cso_cache
• sampler_list : st_context
• sampler_state_pointer : brw_gs_unit_state , brw_vs_unit_state , brw_wm_unit_state
• sampler_texture : st_context
• sampler_textures : st_context
• sampler_unit : aaline_fragment_shader , pstip_fragment_shader
• samplers : cso_context , pstip_stage , quad_shade_stage , st_context
• Samplers : tgsi_exec_machine , spu_exec_machine , brw_context
• samplers_saved : cso_context
• samplersUsed : aa_transform_context , pstip_transform_context
• sanitize_cb : cso_cache
• sanitize_data : cso_cache
• sarea : intel_context , intel_screen
• sarea_priv_offset : drmI830Init , _I830DRIRec
• saturate : brw_instruction
• Saturate : ureg_dst , tgsi_instruction
• sc : i915_rasterizer_state
• scale : offset_stage , pipe_viewport_state
• Scale2X : tgsi_src_register_ext_mod
• scaleAndBias : state_key
• scissor : brw_sf_viewport , softpipe_context , pipe_rasterizer_state , st_context
• Scissor : brw_context
• scissor : cell_context , failover_context , i915_context , brw_sf_unit_state
• scratch_buffer : brw_context
• scratch_buffer_size : brw_context
• scratch_space_base_pointer : thread2
• screen : i915_screen , brw_screen , softpipe_tile_cache , trace_screen , pipe_context , pipe_texture , st_device , intel_be_device , xlib_egl_driver , stw_device
• screen_create : st_winsys
• screens : drm_driver
• second : aub_file_header
• selectedEvents : xmesa_buffer
• SelectEvent : _glxapi_table
• SelectEventSGIX : _glxapi_table
• selection_stage : st_context
• Semantic : tgsi_full_declaration , tgsi_declaration
• semantic_index : draw_context , ureg_program
• semantic_name : draw_context , ureg_program
• SemanticIndex : tgsi_declaration_semantic
• SemanticName : tgsi_declaration_semantic
• send_commit_msg : brw_instruction
• serialNo : translated_vertex_program , st_fragment_program , st_vertex_program
• Set3DfxModeMESA : _glxapi_table
• set_blend_color : pipe_context
• set_buffer : draw_vs_varient , translate
• set_clip_state : pipe_context
• set_constant_buffer : pipe_context
• set_edgeflags : pipe_context
• set_framebuffer_state : pipe_context
• set_polygon_stipple : pipe_context
• set_primitive : vbuf_render
• set_sampler_textures : pipe_context
• set_scissor_state : pipe_context
• set_vertex_buffers : pipe_context
• set_vertex_elements : pipe_context
• set_viewport_state : pipe_context
• setStatus : _DriBufferPool
• setup : softpipe_context , setup_stage
• sf : brw_context , brw_binding_table_pointers , brw_pipelined_state_pointers
• sf5 : brw_sf_unit_state
• sf6 : brw_sf_unit_state
• sf7 : brw_sf_unit_state
• sf_fence : brw_urb_fence
• sf_realloc : brw_urb_fence
• sf_start : brw_context
• sf_viewport_state_offset : brw_sf_unit_state
• sfsize : brw_context
• shade : softpipe_context
• shader : draw_vs_varient_generic , cell_vertex_shader_state , cell_fragment_shader_state , i915_fp_compile , sp_fragment_shader , sp_vertex_shader
• shadow_ambient : pipe_sampler_state
• shadow_function : brw_sampler_state
• shadowtex_mask : brw_wm_prog_key
• shm : xm_buffer , xmesa_pipe_winsys , xmesa_buffer
• shown : drm_screen
• sign : twoside_stage
• signaled : _DriFenceMgrCreateInfo
• signaled_type : _DriFenceObject
• single_program_flow : brw_compile , thread1 , brw_clip_unit_state
• size : cso_hash_data , vertex_info , mm_pb_manager , pb_validate , ureg_tokens , debug_memory_header , util_cache , handle_table , mem_block , cell_array_info , cell_attribute_fetch_code , cell_buffer_range , spu_vs_context , i915_batchbuffer , brw_mem_pool , brw_cache , pipe_format_block , pipe_buffer , pipe_constant_buffer , _DriBufferPool , intel_screen , drmI830MemAlloc , drmI830MemInitHeap , aub_buffer , aub_pipe_winsys , st_buffer_object , pipe_format_info
• Size : tgsi_token , tgsi_declaration , tgsi_immediate , tgsi_instruction
• sizes : brw_vertex_info
• slab : pb_slab_buffer
• slabPool : _DriSlabSizeHeader
• slabs : pb_slab_manager , _DriSlabSizeHeader
• slabSize : pb_slab_manager
• slabTimeout : _DriFreeSlabManager
• slot : draw_context
• softpipe : softpipe_vbuf_render , quad_stage , setup_context
• source_depth_reg : brw_wm_prog_key
• source_depth_to_render_target : brw_wm_prog_key
• span : setup_stage , setup_context
• spe_contexts : cell_global_info
• spe_threads : cell_global_info
• spec_attribs : flat_stage
• sprite_coord_mode : pipe_rasterizer_state
• sprite_fs : aaline_fragment_shader
• sprite_point : brw_sf_unit_state
• src : fetch_shade_emit , tgsi_any_token
• src0_abs : brw_instruction
• src0_address_mode : brw_instruction
• src0_horiz_stride : brw_instruction
• src0_indirect_offset : brw_instruction
• src0_negate : brw_instruction
• src0_reg_file : brw_instruction
• src0_reg_nr : brw_instruction
• src0_reg_type : brw_instruction
• src0_subreg_nr : brw_instruction
• src0_swz_w : brw_instruction
• src0_swz_x : brw_instruction
• src0_swz_y : brw_instruction
• src0_swz_z : brw_instruction
• src0_vert_stride : brw_instruction
• src0_width : brw_instruction
• src1_abs : brw_instruction
• src1_horiz_stride : brw_instruction
• src1_indirect_offset : brw_instruction
• src1_negate : brw_instruction
• src1_reg_file : brw_instruction
• src1_reg_nr : brw_instruction
• src1_reg_type : brw_instruction
• src1_subreg_nr : brw_instruction
• src1_swz_w : brw_instruction
• src1_swz_x : brw_instruction
• src1_swz_y : brw_instruction
• src1_swz_z : brw_instruction
• src1_vert_stride : brw_instruction
• src1_width : brw_instruction
• src_blend_factor : brw_cc_unit_state
• src_ext_mod : tgsi_any_token
• src_ext_swz : tgsi_any_token
• src_format : brw_vertex_element_state , pipe_vertex_element
• src_index : vertex_info
• src_offset : brw_vertex_element_state , pipe_vertex_element
• src_ptr : spu_vs_context
• SrcRegister : tgsi_full_src_register
• SrcRegisterDim : tgsi_full_src_register
• SrcRegisterDimInd : tgsi_full_src_register
• SrcRegisterExtMod : tgsi_full_src_register
• SrcRegisterExtSwz : tgsi_full_src_register
• SrcRegisterInd : tgsi_full_src_register
• ss0 : brw_sampler_state , brw_surface_state
• ss1 : brw_surface_state , brw_sampler_state
• ss2 : brw_sampler_state , brw_surface_state
• ss3 : brw_surface_state , brw_sampler_state
• ss4 : brw_surface_state
• st : i915_rasterizer_state , intel_context , xmesa_context , st_state_flags , wgl_context
• st_dev : st_context , st_buffer
• st_ws : st_device
• stack : brw_compile , brw_wm_compile , brw_vs_compile
• stack_index : brw_wm_compile
• stage : twoside_stage , rastpos_stage , aaline_stage , unfilled_stage , clipper , cull_stage , flat_stage , setup_stage , quad_shade_stage , pstip_stage , feedback_stage , render_stage , vbuf_stage , widepoint_stage , wideline_stage , aapoint_stage , stipple_stage , offset_stage
• start : translate , pb_slab_buffer , softpipe_query , draw_vs_varient , pool_buffer , cell_command_texture , drmI830BatchBuffer , drmI830MemInitHeap , spu_texture , _DriSlabBuffer
• start_addr : brw_vertex_buffer_state
• start_instance_location : brw_3d_primitive
• start_vert_location : brw_3d_primitive
• state : cso_fragment_shader , cso_vertex_shader , cso_sampler , aaline_stage , draw_vertex_shader , cell_command_sampler , i915_fragment_shader , st_fragment_program , st_vertex_program , cso_blend , aapoint_fragment_shader , brw_context , cso_depth_stencil_alpha , st_context , tgsi_sampler , i915_sampler_state , spu_sampler , pstip_fragment_shader , pstip_stage , aaline_fragment_shader , cso_rasterizer
• state_gs_offset : brw_context
• staticPool : intel_be_device
• statistics_enable : brw_vf_statistics , brw_cc_unit_state
• stats_enable : brw_clip_unit_state , brw_gs_unit_state , brw_wm_unit_state , brw_sf_unit_state , brw_vs_unit_state
• status : pipe_surface
• stencil : pipe_depth_stencil_alpha_state
• stencil8 : softpipe_cached_tile
• stencil_bits : pipe_format_info
• stencil_enable : brw_cc_unit_state
• stencil_fail_op : brw_cc_unit_state
• stencil_func : brw_cc_unit_state
• stencil_LIS5 : i915_depth_stencil_state
• stencil_modes4 : i915_depth_stencil_state
• stencil_pass_depth_fail_op : brw_cc_unit_state
• stencil_pass_depth_pass_op : brw_cc_unit_state
• stencil_ref : brw_cc_unit_state
• stencil_test : softpipe_context
• stencil_test_mask : brw_cc_unit_state
• stencil_write_enable : brw_cc_unit_state
• stencil_write_mask : brw_cc_unit_state
• stencilbits : pixelformat_depth_info
• stfb : xmesa_buffer , intel_framebuffer , stw_framebuffer , intel_framebuffer
• stipple : pipe_poly_stipple , draw_context , pstip_stage , brw_polygon_stipple
• store : brw_compile , spe_function
• str : str_dump_ctx , util_strbuf
• stride : cell_texture , pipe_surface , brw_texture , i915_texture , softpipe_texture
• stw_winsys : stw_device
• subnr : brw_reg
• subpixel_precision : brw_sf_unit_state
• surf : bitmap_cache , drm_screen
• surf_ss_offset : brw_surface_binding_table
• surface : st_renderbuffer , cell_command_clear_surface , st_texture_image , intel_screen , trace_surface , sct_surface , softpipe_tile_cache
• surface_alloc : pipe_winsys
• surface_alloc_storage : pipe_winsys
• surface_copy : pipe_context
• surface_fill : pipe_context
• surface_format : brw_surface_state
• surface_map : softpipe_tile_cache , pipe_screen
• surface_release : pipe_winsys
• surface_save : st_renderbuffer
• surface_state_address : brw_state_base_address
• surface_state_type : aub_block_header
• surface_type : brw_surface_state , brw_depthbuffer
• surface_unmap : pipe_screen
• surfaces : surface_context_tracker , sct_context
• suspend_flushing : draw_context
• sw : failover_context
• sw_exception_enable : brw_clip_unit_state , thread1
• sw_sampler_state : failover_context
• sw_state : fo_state
• SwapBuffers : _glxapi_table
• SwapIntervalSGI : _glxapi_table
• swizzle : brw_reg
• swizzle_control : brw_urb_immediate
• SwizzleW : tgsi_src_register , ureg_src
• SwizzleX : tgsi_src_register , ureg_src
• SwizzleY : tgsi_src_register , ureg_src
• SwizzleZ : ureg_src , tgsi_src_register
• sws : intel_softpipe_winsys
• sx : edge
• sy : edge
• system_instruction_pointer : brw_system_instruction_pointer
• sz : brw_cached_batch_item , drmI830CmdBuffer

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