- m -

• m00 : brw_sf_viewport
• m11 : brw_sf_viewport
• m1Cx : brw_sf_compile
• m22 : brw_sf_viewport
• m2Cy : brw_sf_compile
• m30 : brw_sf_viewport
• m31 : brw_sf_viewport
• m32 : brw_sf_viewport
• m3C0 : brw_sf_compile
• m_addresses : StorageSoa
• m_addrs : Storage
• m_argStack : Storage
• m_block : Storage , StorageSoa
• m_builder : InstructionsSoa , Instructions
• m_builtinDependencies : InstructionsSoa
• m_builtins : InstructionsSoa
• m_constInts : Storage , StorageSoa
• m_consts : StorageSoa
• m_destWriteMap : Storage
• m_extSwizzleVec : Storage
• m_floatVecType : Instructions , Storage
• m_fmtPtr : Instructions
• m_func : Instructions
• m_functions : Instructions , InstructionsSoa
• m_functionsMap : InstructionsSoa
• m_idx : InstructionsSoa , Storage , StorageSoa , Instructions
• m_ifStack : Instructions
• m_immediates : Storage , StorageSoa
• m_immediatesToFlush : StorageSoa
• m_INPUT : Storage
• m_input : StorageSoa
• m_intVecs : Storage
• m_intVecType : Storage
• m_llvmCeil : Instructions
• m_llvmFAbs : Instructions
• m_llvmFexp : Instructions
• m_llvmFlog : Instructions
• m_llvmFloor : Instructions
• m_llvmFSqrt : Instructions
• m_llvmLit : Instructions
• m_llvmPow : Instructions
• m_loopStack : Instructions
• m_mod : Instructions
• m_name : Instructions , InstructionsSoa , Storage , StorageSoa
• m_numConsts : Storage
• m_output : StorageSoa
• m_storage : Instructions , InstructionsSoa
• m_temps : StorageSoa
• m_tempStack : Storage
• m_tempWriteMap : Storage
• m_undefFloatVec : Storage
• m_undefIntVec : Storage
• machine : draw_context , exec_vertex_shader , draw_llvm_vertex_shader , spu_vs_context , quad_shade_stage
• mag_filter : brw_sampler_state
• mag_img_filter : pipe_sampler_state
• magic : debug_memory_header , debug_memory_footer
• major : aub_file_header
• MajorVersion : tgsi_version
• MakeContextCurrent : _glxapi_table
• MakeCurrent : _glxapi_table
• MakeCurrentReadSGI : _glxapi_table
• mallocPool : intel_be_device
• map : pb_vtbl , mm_pb_manager , pool_pb_manager , i915_batchbuffer , trace_surface , _DriBufferPool , intel_screen
• map_count : aub_buffer
• mapcount : fenced_buffer
• mapCount : pb_slab_buffer , _DriSlabBuffer
• mapped : st_softpipe_buffer , gdi_softpipe_buffer , xm_buffer
• Mapped : sw_pipe_buffer
• mapped_constants : cell_context , softpipe_context
• mapped_vbuffer : softpipe_context
• mask : setup_stage , quad_header_inout , setup_context
• mask_control : brw_instruction
• mask_stack_exception_enable : thread1 , brw_clip_unit_state
• master : translated_vertex_program
• math : brw_instruction
• max_aniso : brw_sampler_state
• max_anisotropy : pipe_sampler_state
• max_batch_size : intel_be_device
• max_const : brw_vs_prog_data , brw_wm_prog_data
• max_depth : brw_cc_viewport
• max_index : draw_context , brw_array_state , brw_vertex_buffer_state , pipe_vertex_buffer
• max_indices : vbuf_stage , vbuf_render
• max_inst : spe_function
• max_lod : brw_sampler_state , pipe_sampler_state
• max_relocs : i915_batchbuffer
• max_size : cso_cache
• max_threads : brw_vs_unit_state , brw_wm_unit_state , brw_gs_unit_state , brw_context , brw_clip_unit_state , brw_sf_unit_state
• max_tokens_out : tgsi_transform_context
• max_vertex_buffer_bytes : vbuf_render
• max_vertex_size : intel_be_device
• max_vertices : vbuf_stage
• max_vp_index : brw_gs_unit_state
• max_vp_output : pipe_setup_linkage
• max_wm_grf : brw_wm_compile
• maxBufSize : pb_slab_range_manager
• maxGeneric : aa_transform_context
• maxInput : pstip_transform_context , aa_transform_context
• maxlod : i915_sampler_state
• maxSlabSize : _DriSlabPool
• maxx : pipe_scissor_state
• maxy : pipe_scissor_state
• mem : _I830DRIRec
• mesa : st_state_flags
• mesa_visual : xmesa_visual
• mgr : mm_buffer , pb_cache_buffer , _DriFenceObject , pool_buffer , pb_slab
• middle : varray_frontend , draw_context , vcache_frontend
• middle_prim : vcache_frontend
• min_array_element : brw_depthbuffer
• min_array_elt : brw_surface_state
• min_depth : brw_cc_viewport
• min_filter : brw_sampler_state
• min_img_filter : pipe_sampler_state
• min_index : draw_context , cell_command_render
• min_lod : pipe_sampler_state , brw_sampler_state , brw_surface_state
• min_mip_filter : pipe_sampler_state
• minBufSize : pb_slab_range_manager
• minlod : i915_sampler_state
• minor : aub_file_header
• MinorVersion : tgsi_version
• minute : aub_file_header
• minx : pipe_scissor_state
• miny : pipe_scissor_state
• mip_count : brw_surface_state
• mip_filter : brw_sampler_state
• mipmap_layout : brw_depthbuffer
• mipmap_layout_mode : brw_surface_state
• missing_textures : st_context
• mmio_offset : drmI830Init
• mnemonic : tgsi_opcode_info
• mode : unfilled_stage , drm_screen , failover_context
• modes4 : i915_blend_state
• modified : softpipe_texture
• modify_enable : brw_state_base_address
• Modulate : tgsi_dst_register_ext_modulate
• module : gallivm_prog , gallivm_ir
• monochrome_filter_height : brw_sampler_state
• monochrome_filter_width : brw_sampler_state
• month : aub_file_header
• mrd : draw_context
• msg_control : brw_instruction
• msg_length : brw_urb_immediate , brw_instruction
• msg_target : brw_urb_immediate , brw_instruction
• msg_type : brw_instruction
• multisample : pipe_rasterizer_state
• mutex : pool_pb_manager , _DriBufferObject , pb_slab_manager , _DriSlabSizeHeader , fenced_buffer_list , pb_cache_manager , _DriFreeSlabManager , _DriFenceObject , mm_pb_manager , _DriFenceMgr

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